Lines Matching refs:mdev_state
129 struct mdev_state {
155 static int mtty_trigger_interrupt(struct mdev_state *mdev_state);
173 static void mtty_create_config_space(struct mdev_state *mdev_state)
176 STORE_LE32((u32 *) &mdev_state->vconfig[0x0], 0x32534348);
179 STORE_LE16((u16 *) &mdev_state->vconfig[0x4], 0x0001);
182 STORE_LE16((u16 *) &mdev_state->vconfig[0x6], 0x0200);
185 mdev_state->vconfig[0x8] = 0x10;
188 mdev_state->vconfig[0x9] = 0x02;
191 mdev_state->vconfig[0xa] = 0x00;
194 mdev_state->vconfig[0xb] = 0x07;
198 STORE_LE32((u32 *) &mdev_state->vconfig[0x10], 0x000001);
199 mdev_state->bar_mask[0] = ~(MTTY_IO_BAR_SIZE) + 1;
201 if (mdev_state->nr_ports == 2) {
203 STORE_LE32((u32 *) &mdev_state->vconfig[0x14], 0x000001);
204 mdev_state->bar_mask[1] = ~(MTTY_IO_BAR_SIZE) + 1;
208 STORE_LE32((u32 *) &mdev_state->vconfig[0x2c], 0x32534348);
210 mdev_state->vconfig[0x34] = 0x00; /* Cap Ptr */
211 mdev_state->vconfig[0x3d] = 0x01; /* interrupt pin (INTA#) */
214 mdev_state->vconfig[0x40] = 0x23;
215 mdev_state->vconfig[0x43] = 0x80;
216 mdev_state->vconfig[0x44] = 0x23;
217 mdev_state->vconfig[0x48] = 0x23;
218 mdev_state->vconfig[0x4c] = 0x23;
220 mdev_state->vconfig[0x60] = 0x50;
221 mdev_state->vconfig[0x61] = 0x43;
222 mdev_state->vconfig[0x62] = 0x49;
223 mdev_state->vconfig[0x63] = 0x20;
224 mdev_state->vconfig[0x64] = 0x53;
225 mdev_state->vconfig[0x65] = 0x65;
226 mdev_state->vconfig[0x66] = 0x72;
227 mdev_state->vconfig[0x67] = 0x69;
228 mdev_state->vconfig[0x68] = 0x61;
229 mdev_state->vconfig[0x69] = 0x6c;
230 mdev_state->vconfig[0x6a] = 0x2f;
231 mdev_state->vconfig[0x6b] = 0x55;
232 mdev_state->vconfig[0x6c] = 0x41;
233 mdev_state->vconfig[0x6d] = 0x52;
234 mdev_state->vconfig[0x6e] = 0x54;
237 static void handle_pci_cfg_write(struct mdev_state *mdev_state, u16 offset,
248 mdev_state->vconfig[0x3c] = buf[0];
263 if ((mdev_state->nr_ports == 1) && (bar_index == 1)) {
264 STORE_LE32(&mdev_state->vconfig[offset], 0);
272 bar_mask = mdev_state->bar_mask[bar_index];
276 cfg_addr |= (mdev_state->vconfig[offset] & 0x3ul);
277 STORE_LE32(&mdev_state->vconfig[offset], cfg_addr);
282 STORE_LE32(&mdev_state->vconfig[offset], 0);
291 static void handle_bar_write(unsigned int index, struct mdev_state *mdev_state,
300 if (mdev_state->s[index].dlab) {
301 mdev_state->s[index].divisor |= data;
305 mutex_lock(&mdev_state->rxtx_lock);
308 if (mdev_state->s[index].rxtx.count <
309 mdev_state->s[index].max_fifo_size) {
310 mdev_state->s[index].rxtx.fifo[
311 mdev_state->s[index].rxtx.head] = data;
312 mdev_state->s[index].rxtx.count++;
313 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.head);
314 mdev_state->s[index].overrun = false;
320 if ((mdev_state->s[index].uart_reg[UART_IER] &
322 (mdev_state->s[index].rxtx.count ==
323 mdev_state->s[index].intr_trigger_level)) {
329 mtty_trigger_interrupt(mdev_state);
335 mdev_state->s[index].overrun = true;
341 if (mdev_state->s[index].uart_reg[UART_IER] &
343 mtty_trigger_interrupt(mdev_state);
345 mutex_unlock(&mdev_state->rxtx_lock);
350 if (mdev_state->s[index].dlab)
351 mdev_state->s[index].divisor |= (u16)data << 8;
353 mdev_state->s[index].uart_reg[offset] = data;
354 mutex_lock(&mdev_state->rxtx_lock);
356 (mdev_state->s[index].rxtx.head ==
357 mdev_state->s[index].rxtx.tail)) {
362 mtty_trigger_interrupt(mdev_state);
365 mutex_unlock(&mdev_state->rxtx_lock);
371 mdev_state->s[index].fcr = data;
373 mutex_lock(&mdev_state->rxtx_lock);
376 mdev_state->s[index].rxtx.count = 0;
377 mdev_state->s[index].rxtx.head = 0;
378 mdev_state->s[index].rxtx.tail = 0;
380 mutex_unlock(&mdev_state->rxtx_lock);
384 mdev_state->s[index].intr_trigger_level = 1;
388 mdev_state->s[index].intr_trigger_level = 4;
392 mdev_state->s[index].intr_trigger_level = 8;
396 mdev_state->s[index].intr_trigger_level = 14;
405 mdev_state->s[index].intr_trigger_level = 1;
407 mdev_state->s[index].max_fifo_size = MAX_FIFO_SIZE;
409 mdev_state->s[index].max_fifo_size = 1;
410 mdev_state->s[index].intr_trigger_level = 1;
417 mdev_state->s[index].dlab = true;
418 mdev_state->s[index].divisor = 0;
420 mdev_state->s[index].dlab = false;
422 mdev_state->s[index].uart_reg[offset] = data;
426 mdev_state->s[index].uart_reg[offset] = data;
428 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
433 mtty_trigger_interrupt(mdev_state);
436 if ((mdev_state->s[index].uart_reg[UART_IER] & UART_IER_MSI) &&
441 mtty_trigger_interrupt(mdev_state);
451 mdev_state->s[index].uart_reg[offset] = data;
459 static void handle_bar_read(unsigned int index, struct mdev_state *mdev_state,
466 if (mdev_state->s[index].dlab) {
467 *buf = (u8)mdev_state->s[index].divisor;
471 mutex_lock(&mdev_state->rxtx_lock);
473 if (mdev_state->s[index].rxtx.head !=
474 mdev_state->s[index].rxtx.tail) {
475 *buf = mdev_state->s[index].rxtx.fifo[
476 mdev_state->s[index].rxtx.tail];
477 mdev_state->s[index].rxtx.count--;
478 CIRCULAR_BUF_INC_IDX(mdev_state->s[index].rxtx.tail);
481 if (mdev_state->s[index].rxtx.head ==
482 mdev_state->s[index].rxtx.tail) {
490 if (mdev_state->s[index].uart_reg[UART_IER] &
492 mtty_trigger_interrupt(mdev_state);
494 mutex_unlock(&mdev_state->rxtx_lock);
499 if (mdev_state->s[index].dlab) {
500 *buf = (u8)(mdev_state->s[index].divisor >> 8);
503 *buf = mdev_state->s[index].uart_reg[offset] & 0x0f;
508 u8 ier = mdev_state->s[index].uart_reg[UART_IER];
511 mutex_lock(&mdev_state->rxtx_lock);
513 if ((ier & UART_IER_RLSI) && mdev_state->s[index].overrun)
518 (mdev_state->s[index].rxtx.count >=
519 mdev_state->s[index].intr_trigger_level))
524 (mdev_state->s[index].rxtx.head ==
525 mdev_state->s[index].rxtx.tail))
530 (mdev_state->s[index].uart_reg[UART_MCR] &
540 mutex_unlock(&mdev_state->rxtx_lock);
546 *buf = mdev_state->s[index].uart_reg[offset];
553 mutex_lock(&mdev_state->rxtx_lock);
555 if (mdev_state->s[index].rxtx.head !=
556 mdev_state->s[index].rxtx.tail)
560 if (mdev_state->s[index].overrun)
564 if (mdev_state->s[index].rxtx.head ==
565 mdev_state->s[index].rxtx.tail)
568 mutex_unlock(&mdev_state->rxtx_lock);
575 mutex_lock(&mdev_state->rxtx_lock);
577 if (mdev_state->s[index].uart_reg[UART_MCR] &
579 if (mdev_state->s[index].rxtx.count <
580 mdev_state->s[index].max_fifo_size)
584 mutex_unlock(&mdev_state->rxtx_lock);
589 *buf = mdev_state->s[index].uart_reg[offset];
597 static void mdev_read_base(struct mdev_state *mdev_state)
607 if (!mdev_state->region_info[index].size)
610 start_lo = (*(u32 *)(mdev_state->vconfig + pos)) &
612 mem_type = (*(u32 *)(mdev_state->vconfig + pos)) &
617 start_hi = (*(u32 *)(mdev_state->vconfig + pos + 4));
629 mdev_state->region_info[index].start = ((u64)start_hi << 32) |
637 struct mdev_state *mdev_state;
645 mdev_state = mdev_get_drvdata(mdev);
646 if (!mdev_state) {
647 pr_err("%s mdev_state not found\n", __func__);
651 mutex_lock(&mdev_state->ops_lock);
664 handle_pci_cfg_write(mdev_state, offset, buf, count);
666 memcpy(buf, (mdev_state->vconfig + offset), count);
673 if (!mdev_state->region_info[index].start)
674 mdev_read_base(mdev_state);
682 *buf, mdev_state->s[index].dlab);
684 handle_bar_write(index, mdev_state, offset, buf, count);
686 handle_bar_read(index, mdev_state, offset, buf, count);
692 *buf, mdev_state->s[index].dlab);
706 mutex_unlock(&mdev_state->ops_lock);
713 struct mdev_state *mdev_state;
732 mdev_state = kzalloc(sizeof(struct mdev_state), GFP_KERNEL);
733 if (mdev_state == NULL)
736 mdev_state->nr_ports = nr_ports;
737 mdev_state->irq_index = -1;
738 mdev_state->s[0].max_fifo_size = MAX_FIFO_SIZE;
739 mdev_state->s[1].max_fifo_size = MAX_FIFO_SIZE;
740 mutex_init(&mdev_state->rxtx_lock);
741 mdev_state->vconfig = kzalloc(MTTY_CONFIG_SPACE_SIZE, GFP_KERNEL);
743 if (mdev_state->vconfig == NULL) {
744 kfree(mdev_state);
748 mutex_init(&mdev_state->ops_lock);
749 mdev_state->mdev = mdev;
750 mdev_set_drvdata(mdev, mdev_state);
752 mtty_create_config_space(mdev_state);
755 list_add(&mdev_state->next, &mdev_devices_list);
763 struct mdev_state *mds, *tmp_mds;
764 struct mdev_state *mdev_state = mdev_get_drvdata(mdev);
769 if (mdev_state == mds) {
770 list_del(&mdev_state->next);
772 kfree(mdev_state->vconfig);
773 kfree(mdev_state);
785 struct mdev_state *mdev_state;
790 mdev_state = mdev_get_drvdata(mdev);
791 if (!mdev_state)
920 struct mdev_state *mdev_state;
925 mdev_state = mdev_get_drvdata(mdev);
926 if (!mdev_state)
929 mutex_lock(&mdev_state->ops_lock);
940 if (mdev_state->intx_evtfd)
941 eventfd_ctx_put(mdev_state->intx_evtfd);
956 mdev_state->intx_evtfd = evt;
957 mdev_state->irq_fd = fd;
958 mdev_state->irq_index = index;
973 if (mdev_state->msi_evtfd)
974 eventfd_ctx_put(mdev_state->msi_evtfd);
976 mdev_state->irq_index = VFIO_PCI_INTX_IRQ_INDEX;
986 if (mdev_state->msi_evtfd)
994 mdev_state->msi_evtfd = evt;
995 mdev_state->irq_fd = fd;
996 mdev_state->irq_index = index;
1012 mutex_unlock(&mdev_state->ops_lock);
1016 static int mtty_trigger_interrupt(struct mdev_state *mdev_state)
1020 if ((mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX) &&
1021 (!mdev_state->msi_evtfd))
1023 else if ((mdev_state->irq_index == VFIO_PCI_INTX_IRQ_INDEX) &&
1024 (!mdev_state->intx_evtfd)) {
1029 if (mdev_state->irq_index == VFIO_PCI_MSI_IRQ_INDEX)
1030 ret = eventfd_signal(mdev_state->msi_evtfd, 1);
1032 ret = eventfd_signal(mdev_state->intx_evtfd, 1);
1048 struct mdev_state *mdev_state;
1054 mdev_state = mdev_get_drvdata(mdev);
1055 if (!mdev_state)
1062 mutex_lock(&mdev_state->ops_lock);
1072 if (mdev_state->nr_ports == 2)
1080 mdev_state->region_info[bar_index].size = size;
1081 mdev_state->region_info[bar_index].vfio_offset =
1088 mutex_unlock(&mdev_state->ops_lock);
1132 struct mdev_state *mdev_state;
1137 mdev_state = mdev_get_drvdata(mdev);
1138 if (!mdev_state)
1158 memcpy(&mdev_state->dev_info, &info, sizeof(info));
1200 (info.index >= mdev_state->dev_info.num_irqs))
1224 mdev_state->dev_info.num_irqs,
1335 struct mdev_state *mds;