Lines Matching refs:DEFINE
66 DEFINE(EMIF_SDCFG_VAL_OFFSET,
68 DEFINE(EMIF_TIMING1_VAL_OFFSET,
70 DEFINE(EMIF_TIMING2_VAL_OFFSET,
72 DEFINE(EMIF_TIMING3_VAL_OFFSET,
74 DEFINE(EMIF_REF_CTRL_VAL_OFFSET,
76 DEFINE(EMIF_ZQCFG_VAL_OFFSET,
78 DEFINE(EMIF_PMCR_VAL_OFFSET,
80 DEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,
82 DEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,
84 DEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,
86 DEFINE(EMIF_COS_CONFIG_OFFSET,
88 DEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,
90 DEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,
92 DEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,
94 DEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,
96 DEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,
98 DEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,
100 DEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,
102 DEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,
104 DEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,
106 DEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,
108 DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));
112 DEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,
114 DEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,
116 DEFINE(EMIF_PM_CONFIG_OFFSET,
118 DEFINE(EMIF_PM_REGS_VIRT_OFFSET,
120 DEFINE(EMIF_PM_REGS_PHYS_OFFSET,
122 DEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));
126 DEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,
128 DEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,
130 DEFINE(EMIF_PM_RUN_HW_LEVELING,
132 DEFINE(EMIF_PM_ENTER_SR_OFFSET,
134 DEFINE(EMIF_PM_EXIT_SR_OFFSET,
136 DEFINE(EMIF_PM_ABORT_SR_OFFSET,
138 DEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));