Lines Matching defs:emif_regs_amx3
23 struct emif_regs_amx3 {
51 struct emif_regs_amx3 *regs_virt;
67 offsetof(struct emif_regs_amx3, emif_sdcfg_val));
69 offsetof(struct emif_regs_amx3, emif_timing1_val));
71 offsetof(struct emif_regs_amx3, emif_timing2_val));
73 offsetof(struct emif_regs_amx3, emif_timing3_val));
75 offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));
77 offsetof(struct emif_regs_amx3, emif_zqcfg_val));
79 offsetof(struct emif_regs_amx3, emif_pmcr_val));
81 offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));
83 offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));
85 offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));
87 offsetof(struct emif_regs_amx3, emif_cos_config));
89 offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));
91 offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));
93 offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));
95 offsetof(struct emif_regs_amx3, emif_ocp_config_val));
97 offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));
99 offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));
101 offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));
103 offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));
105 offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));
107 offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));
108 DEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));