Lines Matching refs:timer
45 /* timer interrupt enable bits */
59 /* timer capabilities used in hwmod database */
67 * timer errata flags
71 * timer counter register is never read. For more details please refer to
125 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
129 int omap_dm_timer_trigger(struct omap_dm_timer *timer);
140 * These registers are offsets from timer->iobase.
156 * These registers are offsets from timer->func_base. The func_base
176 #define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
255 static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
259 while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
262 return readl_relaxed(timer->func_base + (reg & 0xff));
265 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
269 while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
272 writel_relaxed(val, timer->func_base + (reg & 0xff));
275 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
280 tidr = readl_relaxed(timer->io_base);
282 timer->revision = 1;
283 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
284 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
285 timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
286 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
287 timer->func_base = timer->io_base;
289 timer->revision = 2;
290 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
291 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
292 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
293 timer->pend = timer->io_base +
296 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
302 * @timer: pointer to timer instance handle
304 * Enables the write posted mode for the timer. When posted mode is enabled
305 * writes to certain timer registers are immediately acknowledged by the
308 * timer registers.
310 static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
312 if (timer->posted)
315 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767) {
316 timer->posted = OMAP_TIMER_NONPOSTED;
317 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 0, 0);
321 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
323 timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
324 timer->posted = OMAP_TIMER_POSTED;
328 * __omap_dm_timer_override_errata - override errata flags for a timer
329 * @timer: pointer to timer handle
332 * For a given timer, override a timer errata by clearing the flags
334 * overridden for a timer if the timer is used in such a way the erratum
337 static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
340 timer->errata &= ~errata;
343 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
348 l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
351 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
354 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
357 * timer is stopped
364 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
367 static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
371 __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
372 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
375 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
378 writel_relaxed(value, timer->irq_ena);
379 __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
383 __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
385 return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
388 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
391 writel_relaxed(value, timer->irq_stat);