Lines Matching refs:wdt
2 * drivers/char/watchdog/sp805-wdt.c
36 #define MODULE_NAME "sp805-wdt"
57 * struct sp805_wdt: sp805 wdt device structure
60 * @base: base address of wdt
61 * @clk: clock structure of wdt
62 * @adev: amba device structure of wdt
63 * @status: current status of wdt
81 /* returns true if wdt is running; otherwise returns false */
84 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
85 u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
93 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
96 rate = wdt->rate;
109 spin_lock(&wdt->lock);
110 wdt->load_val = load;
113 spin_unlock(&wdt->lock);
121 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
124 spin_lock(&wdt->lock);
125 load = readl_relaxed(wdt->base + WDTVALUE);
128 if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
129 load += wdt->load_val + 1;
130 spin_unlock(&wdt->lock);
132 return div_u64(load, wdt->rate);
138 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
140 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
141 writel_relaxed(0, wdt->base + WDTCONTROL);
142 writel_relaxed(0, wdt->base + WDTLOAD);
143 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
146 readl_relaxed(wdt->base + WDTLOCK);
153 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
158 ret = clk_prepare_enable(wdt->clk);
160 dev_err(&wdt->adev->dev, "clock enable fail");
165 spin_lock(&wdt->lock);
167 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
168 writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
169 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
172 writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
175 writel_relaxed(LOCK, wdt->base + WDTLOCK);
178 readl_relaxed(wdt->base + WDTLOCK);
179 spin_unlock(&wdt->lock);
198 struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
200 spin_lock(&wdt->lock);
202 writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
203 writel_relaxed(0, wdt->base + WDTCONTROL);
204 writel_relaxed(LOCK, wdt->base + WDTLOCK);
207 readl_relaxed(wdt->base + WDTLOCK);
208 spin_unlock(&wdt->lock);
210 clk_disable_unprepare(wdt->clk);
233 struct sp805_wdt *wdt;
236 wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
237 if (!wdt) {
242 wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
243 if (IS_ERR(wdt->base))
244 return PTR_ERR(wdt->base);
247 wdt->clk = devm_clk_get(&adev->dev, NULL);
248 if (IS_ERR(wdt->clk)) {
250 return PTR_ERR(wdt->clk);
252 wdt->rate = clk_get_rate(wdt->clk);
260 &wdt->rate);
261 if (!wdt->rate) {
267 wdt->adev = adev;
268 wdt->wdd.info = &wdt_info;
269 wdt->wdd.ops = &wdt_ops;
270 wdt->wdd.parent = &adev->dev;
272 spin_lock_init(&wdt->lock);
273 watchdog_set_nowayout(&wdt->wdd, nowayout);
274 watchdog_set_drvdata(&wdt->wdd, wdt);
275 watchdog_set_restart_priority(&wdt->wdd, 128);
281 wdt->wdd.timeout = DEFAULT_TIMEOUT;
282 watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
283 wdt_setload(&wdt->wdd, wdt->wdd.timeout);
286 * If HW is already running, enable/reset the wdt and set the running
287 * bit to tell the wdt subsystem
289 if (wdt_is_running(&wdt->wdd)) {
290 wdt_enable(&wdt->wdd);
291 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
294 ret = watchdog_register_device(&wdt->wdd);
297 amba_set_drvdata(adev, wdt);
309 struct sp805_wdt *wdt = amba_get_drvdata(adev);
311 watchdog_unregister_device(&wdt->wdd);
312 watchdog_set_drvdata(&wdt->wdd, NULL);
317 struct sp805_wdt *wdt = dev_get_drvdata(dev);
319 if (watchdog_active(&wdt->wdd))
320 return wdt_disable(&wdt->wdd);
327 struct sp805_wdt *wdt = dev_get_drvdata(dev);
329 if (watchdog_active(&wdt->wdd))
330 return wdt_enable(&wdt->wdd);