Lines Matching refs:val
101 u32 val;
103 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
104 val |= SP5100_WDT_START_STOP_BIT;
105 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
108 val |= SP5100_WDT_TRIGGER_BIT;
109 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
117 u32 val;
119 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
120 val &= ~SP5100_WDT_START_STOP_BIT;
121 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
129 u32 val;
131 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
132 val |= SP5100_WDT_TRIGGER_BIT;
133 writel(val, SP5100_WDT_CONTROL(tco->tcobase));
159 u8 val;
162 val = inb(SP5100_IO_PM_DATA_REG);
163 val &= reset;
164 val |= set;
165 outb(val, SP5100_IO_PM_DATA_REG);
170 u32 val;
189 &val);
191 val |= SP5100_PCI_WATCHDOG_DECODE_EN;
195 val);
213 u32 val = 0;
217 val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
219 return val;
227 u32 mmio_addr = 0, val;
260 val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
261 if (!(val & EFCH_PM_DECODEEN_WDT_TMREN)) {
266 val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
267 if (val & EFCH_PM_DECODEEN_WDT_TMREN)
314 val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
315 if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
347 val = readl(SP5100_WDT_CONTROL(tco->tcobase));
348 if (val & SP5100_WDT_DISABLED) {
358 if (val & SP5100_WDT_FIRED)
361 val &= ~SP5100_WDT_ACTION_RESET;
362 writel(val, SP5100_WDT_CONTROL(tco->tcobase));