Lines Matching refs:wdt
164 { .compatible = "samsung,s3c2410-wdt",
166 { .compatible = "samsung,s3c6410-wdt",
168 { .compatible = "samsung,exynos5250-wdt",
170 { .compatible = "samsung,exynos5420-wdt",
172 { .compatible = "samsung,exynos7-wdt",
181 .name = "s3c2410-wdt",
203 static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
206 u32 mask_val = 1 << wdt->drv_data->mask_bit;
210 if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
216 ret = regmap_update_bits(wdt->pmureg,
217 wdt->drv_data->disable_reg,
222 ret = regmap_update_bits(wdt->pmureg,
223 wdt->drv_data->mask_reset_reg,
227 dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
234 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
236 spin_lock(&wdt->lock);
237 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
238 spin_unlock(&wdt->lock);
243 static void __s3c2410wdt_stop(struct s3c2410_wdt *wdt)
247 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
249 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
254 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
256 spin_lock(&wdt->lock);
257 __s3c2410wdt_stop(wdt);
258 spin_unlock(&wdt->lock);
266 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
268 spin_lock(&wdt->lock);
270 __s3c2410wdt_stop(wdt);
272 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
283 dev_dbg(wdt->dev, "Starting watchdog: count=0x%08x, wtcon=%08lx\n",
284 wdt->count, wtcon);
286 writel(wdt->count, wdt->reg_base + S3C2410_WTDAT);
287 writel(wdt->count, wdt->reg_base + S3C2410_WTCNT);
288 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
289 spin_unlock(&wdt->lock);
294 static inline int s3c2410wdt_is_running(struct s3c2410_wdt *wdt)
296 return readl(wdt->reg_base + S3C2410_WTCON) & S3C2410_WTCON_ENABLE;
302 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
303 unsigned long freq = clk_get_rate(wdt->clock);
314 dev_dbg(wdt->dev, "Heartbeat: count=%d, timeout=%d, freq=%lu\n",
326 dev_err(wdt->dev, "timeout %d too big\n", timeout);
331 dev_dbg(wdt->dev, "Heartbeat: timeout=%d, divisor=%d, count=%d (%08x)\n",
335 wdt->count = count;
338 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
342 writel(count, wdt->reg_base + S3C2410_WTDAT);
343 writel(wtcon, wdt->reg_base + S3C2410_WTCON);
353 struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
354 void __iomem *wdt_base = wdt->reg_base;
401 struct s3c2410_wdt *wdt = platform_get_drvdata(param);
403 dev_info(wdt->dev, "watchdog timer expired (irq)\n");
405 s3c2410wdt_keepalive(&wdt->wdt_device);
407 if (wdt->drv_data->quirks & QUIRK_HAS_WTCLRINT_REG)
408 writel(0x1, wdt->reg_base + S3C2410_WTCLRINT);
419 struct s3c2410_wdt *wdt = freq_to_wdt(nb);
421 if (!s3c2410wdt_is_running(wdt))
430 s3c2410wdt_keepalive(&wdt->wdt_device);
432 s3c2410wdt_stop(&wdt->wdt_device);
434 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
435 wdt->wdt_device.timeout);
438 s3c2410wdt_start(&wdt->wdt_device);
447 dev_err(wdt->dev, "cannot set new value for timeout %d\n",
448 wdt->wdt_device.timeout);
452 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
454 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
456 return cpufreq_register_notifier(&wdt->freq_transition,
460 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
462 wdt->freq_transition.notifier_call = s3c2410wdt_cpufreq_transition;
464 cpufreq_unregister_notifier(&wdt->freq_transition,
470 static inline int s3c2410wdt_cpufreq_register(struct s3c2410_wdt *wdt)
475 static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt)
480 static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt)
485 if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT))
488 ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat);
490 dev_warn(wdt->dev, "Couldn't get RST_STAT register\n");
491 else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit))
515 struct s3c2410_wdt *wdt;
521 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
522 if (!wdt)
525 wdt->dev = dev;
526 spin_lock_init(&wdt->lock);
527 wdt->wdt_device = s3c2410_wdd;
529 wdt->drv_data = s3c2410_get_wdt_drv_data(pdev);
530 if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
531 wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
533 if (IS_ERR(wdt->pmureg)) {
535 return PTR_ERR(wdt->pmureg);
547 wdt->reg_base = devm_platform_ioremap_resource(pdev, 0);
548 if (IS_ERR(wdt->reg_base)) {
549 ret = PTR_ERR(wdt->reg_base);
553 wdt->clock = devm_clk_get(dev, "watchdog");
554 if (IS_ERR(wdt->clock)) {
556 ret = PTR_ERR(wdt->clock);
560 ret = clk_prepare_enable(wdt->clock);
566 wdt->wdt_device.min_timeout = 1;
567 wdt->wdt_device.max_timeout = s3c2410wdt_max_timeout(wdt->clock);
569 ret = s3c2410wdt_cpufreq_register(wdt);
575 watchdog_set_drvdata(&wdt->wdt_device, wdt);
580 watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
581 ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
582 wdt->wdt_device.timeout);
584 started = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
602 watchdog_set_nowayout(&wdt->wdt_device, nowayout);
603 watchdog_set_restart_priority(&wdt->wdt_device, 128);
605 wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
606 wdt->wdt_device.parent = dev;
608 ret = watchdog_register_device(&wdt->wdt_device);
612 ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
618 s3c2410wdt_start(&wdt->wdt_device);
624 s3c2410wdt_stop(&wdt->wdt_device);
627 platform_set_drvdata(pdev, wdt);
631 wtcon = readl(wdt->reg_base + S3C2410_WTCON);
641 watchdog_unregister_device(&wdt->wdt_device);
644 s3c2410wdt_cpufreq_deregister(wdt);
647 clk_disable_unprepare(wdt->clock);
656 struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
658 ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
662 watchdog_unregister_device(&wdt->wdt_device);
664 s3c2410wdt_cpufreq_deregister(wdt);
666 clk_disable_unprepare(wdt->clock);
673 struct s3c2410_wdt *wdt = platform_get_drvdata(dev);
675 s3c2410wdt_mask_and_disable_reset(wdt, true);
677 s3c2410wdt_stop(&wdt->wdt_device);
685 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
688 wdt->wtcon_save = readl(wdt->reg_base + S3C2410_WTCON);
689 wdt->wtdat_save = readl(wdt->reg_base + S3C2410_WTDAT);
691 ret = s3c2410wdt_mask_and_disable_reset(wdt, true);
696 s3c2410wdt_stop(&wdt->wdt_device);
704 struct s3c2410_wdt *wdt = dev_get_drvdata(dev);
707 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTDAT);
708 writel(wdt->wtdat_save, wdt->reg_base + S3C2410_WTCNT);/* Reset count */
709 writel(wdt->wtcon_save, wdt->reg_base + S3C2410_WTCON);
711 ret = s3c2410wdt_mask_and_disable_reset(wdt, false);
716 (wdt->wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis");
731 .name = "s3c2410-wdt",