Lines Matching defs:dw_wdt
83 struct dw_wdt {
101 #define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
103 static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
105 return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
109 static void dw_wdt_update_mode(struct dw_wdt *dw_wdt, enum dw_wdt_rmod rmod)
113 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
118 writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
120 dw_wdt->rmod = rmod;
123 static unsigned int dw_wdt_find_best_top(struct dw_wdt *dw_wdt,
134 if (dw_wdt->timeouts[idx].sec >= timeout)
141 *top_val = dw_wdt->timeouts[idx].top_val;
143 return dw_wdt->timeouts[idx].sec;
146 static unsigned int dw_wdt_get_min_timeout(struct dw_wdt *dw_wdt)
155 if (dw_wdt->timeouts[idx].sec)
159 return dw_wdt->timeouts[idx].sec;
162 static unsigned int dw_wdt_get_max_timeout_ms(struct dw_wdt *dw_wdt)
164 struct dw_wdt_timeout *timeout = &dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1];
172 static unsigned int dw_wdt_get_timeout(struct dw_wdt *dw_wdt)
174 int top_val = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
178 if (dw_wdt->timeouts[idx].top_val == top_val)
186 return dw_wdt->timeouts[idx].sec * dw_wdt->rmod;
191 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
193 writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
201 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
213 timeout = dw_wdt_find_best_top(dw_wdt, DIV_ROUND_UP(top_s, dw_wdt->rmod),
215 if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
221 * Set the new value in the watchdog. Some versions of dw_wdt
227 dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
239 wdd->timeout = timeout * dw_wdt->rmod;
248 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
255 dw_wdt_update_mode(dw_wdt, req ? DW_WDT_RMOD_IRQ : DW_WDT_RMOD_RESET);
261 static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
263 u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
266 if (dw_wdt->rmod == DW_WDT_RMOD_IRQ)
272 writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
277 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
280 dw_wdt_ping(&dw_wdt->wdd);
281 dw_wdt_arm_system_reset(dw_wdt);
288 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
290 if (!dw_wdt->rst) {
295 reset_control_assert(dw_wdt->rst);
296 reset_control_deassert(dw_wdt->rst);
304 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
306 writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
307 dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
308 if (dw_wdt_is_enabled(dw_wdt))
310 dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
312 dw_wdt_arm_system_reset(dw_wdt);
322 struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
326 val = readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET);
327 sec = val / dw_wdt->rate;
329 if (dw_wdt->rmod == DW_WDT_RMOD_IRQ) {
330 val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
363 struct dw_wdt *dw_wdt = devid;
370 val = readl(dw_wdt->regs + WDOG_INTERRUPT_STATUS_REG_OFFSET);
374 watchdog_notify_pretimeout(&dw_wdt->wdd);
382 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
384 dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
385 dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
387 clk_disable_unprepare(dw_wdt->pclk);
388 clk_disable_unprepare(dw_wdt->clk);
395 struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
396 int err = clk_prepare_enable(dw_wdt->clk);
401 err = clk_prepare_enable(dw_wdt->pclk);
403 clk_disable_unprepare(dw_wdt->clk);
407 writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
408 writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
410 dw_wdt_ping(&dw_wdt->wdd);
426 static void dw_wdt_handle_tops(struct dw_wdt *dw_wdt, const u32 *tops)
440 tout.sec = tops[val] / dw_wdt->rate;
442 do_div(msec, dw_wdt->rate);
450 dst = &dw_wdt->timeouts[tidx];
458 dw_wdt->timeouts[val] = tout;
462 static int dw_wdt_init_timeouts(struct dw_wdt *dw_wdt, struct device *dev)
473 data = readl(dw_wdt->regs + WDOG_COMP_PARAMS_1_REG_OFFSET);
489 dw_wdt_handle_tops(dw_wdt, tops);
490 if (!dw_wdt->timeouts[DW_WDT_NUM_TOPS - 1].sec) {
521 static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt)
523 struct device *dev = dw_wdt->wdd.parent;
532 regset->base = dw_wdt->regs;
534 dw_wdt->dbgfs_dir = debugfs_create_dir(dev_name(dev), NULL);
536 debugfs_create_regset32("registers", 0444, dw_wdt->dbgfs_dir, regset);
539 static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt)
541 debugfs_remove_recursive(dw_wdt->dbgfs_dir);
546 static void dw_wdt_dbgfs_init(struct dw_wdt *dw_wdt) {}
547 static void dw_wdt_dbgfs_clear(struct dw_wdt *dw_wdt) {}
555 struct dw_wdt *dw_wdt;
558 dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
559 if (!dw_wdt)
562 dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
563 if (IS_ERR(dw_wdt->regs))
564 return PTR_ERR(dw_wdt->regs);
572 dw_wdt->clk = devm_clk_get(dev, "tclk");
573 if (IS_ERR(dw_wdt->clk)) {
574 dw_wdt->clk = devm_clk_get(dev, NULL);
575 if (IS_ERR(dw_wdt->clk))
576 return PTR_ERR(dw_wdt->clk);
579 ret = clk_prepare_enable(dw_wdt->clk);
583 dw_wdt->rate = clk_get_rate(dw_wdt->clk);
584 if (dw_wdt->rate == 0) {
596 dw_wdt->pclk = devm_clk_get_optional(dev, "pclk");
597 if (IS_ERR(dw_wdt->pclk)) {
598 ret = PTR_ERR(dw_wdt->pclk);
602 ret = clk_prepare_enable(dw_wdt->pclk);
606 dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
607 if (IS_ERR(dw_wdt->rst)) {
608 ret = PTR_ERR(dw_wdt->rst);
613 dw_wdt_update_mode(dw_wdt, DW_WDT_RMOD_RESET);
625 pdev->name, dw_wdt);
629 dw_wdt->wdd.info = &dw_wdt_pt_ident;
634 dw_wdt->wdd.info = &dw_wdt_ident;
637 reset_control_deassert(dw_wdt->rst);
639 ret = dw_wdt_init_timeouts(dw_wdt, dev);
643 wdd = &dw_wdt->wdd;
645 wdd->min_timeout = dw_wdt_get_min_timeout(dw_wdt);
646 wdd->max_hw_heartbeat_ms = dw_wdt_get_max_timeout_ms(dw_wdt);
649 watchdog_set_drvdata(wdd, dw_wdt);
658 if (dw_wdt_is_enabled(dw_wdt)) {
659 wdd->timeout = dw_wdt_get_timeout(dw_wdt);
666 platform_set_drvdata(pdev, dw_wdt);
674 dw_wdt_dbgfs_init(dw_wdt);
679 reset_control_assert(dw_wdt->rst);
682 clk_disable_unprepare(dw_wdt->pclk);
685 clk_disable_unprepare(dw_wdt->clk);
691 struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
693 dw_wdt_dbgfs_clear(dw_wdt);
695 watchdog_unregister_device(&dw_wdt->wdd);
696 reset_control_assert(dw_wdt->rst);
697 clk_disable_unprepare(dw_wdt->pclk);
698 clk_disable_unprepare(dw_wdt->clk);
715 .name = "dw_wdt",