Lines Matching refs:port
27 static int port = 0x91;
68 outb(1, port + CPU5WDT_TRIGGER_REG);
97 outb(0, port + CPU5WDT_TIME_A_REG);
98 outb(0, port + CPU5WDT_TIME_B_REG);
99 outb(1, port + CPU5WDT_MODE_REG);
100 outb(0, port + CPU5WDT_RESET_REG);
101 outb(0, port + CPU5WDT_ENABLE_REG);
155 value = inb(port + CPU5WDT_STATUS_REG);
210 pr_debug("port=0x%x, verbose=%i\n", port, verbose);
217 if (!request_region(port, CPU5WDT_EXTENT, PFX)) {
224 val = inb(port + CPU5WDT_STATUS_REG);
240 release_region(port, CPU5WDT_EXTENT);
260 release_region(port, CPU5WDT_EXTENT);
279 module_param_hw(port, int, ioport, 0);
280 MODULE_PARM_DESC(port, "base address of watchdog card, default is 0x91");