Lines Matching refs:dev
85 static u64 get_counter_value(struct armada_37xx_watchdog *dev, int id)
93 val = readl(dev->reg + CNTR_COUNT_LOW(id));
94 val |= ((u64)readl(dev->reg + CNTR_COUNT_HIGH(id))) << 32;
99 static void set_counter_value(struct armada_37xx_watchdog *dev, int id, u64 val)
101 writel(val & 0xffffffff, dev->reg + CNTR_COUNT_LOW(id));
102 writel(val >> 32, dev->reg + CNTR_COUNT_HIGH(id));
105 static void counter_enable(struct armada_37xx_watchdog *dev, int id)
109 reg = readl(dev->reg + CNTR_CTRL(id));
111 writel(reg, dev->reg + CNTR_CTRL(id));
114 static void counter_disable(struct armada_37xx_watchdog *dev, int id)
118 reg = readl(dev->reg + CNTR_CTRL(id));
120 writel(reg, dev->reg + CNTR_CTRL(id));
123 static void init_counter(struct armada_37xx_watchdog *dev, int id, u32 mode,
128 reg = readl(dev->reg + CNTR_CTRL(id));
142 writel(reg, dev->reg + CNTR_CTRL(id));
147 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
150 counter_disable(dev, CNTR_ID_RETRIGGER);
151 counter_enable(dev, CNTR_ID_RETRIGGER);
158 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
161 res = get_counter_value(dev, CNTR_ID_WDOG) * CNTR_CTRL_PRESCALE_MIN;
162 do_div(res, dev->clk_rate);
170 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
179 dev->timeout = (u64)dev->clk_rate * timeout;
180 do_div(dev->timeout, CNTR_CTRL_PRESCALE_MIN);
185 static bool armada_37xx_wdt_is_running(struct armada_37xx_watchdog *dev)
189 regmap_read(dev->cpu_misc, WDT_TIMER_SELECT, ®);
193 reg = readl(dev->reg + CNTR_CTRL(CNTR_ID_WDOG));
199 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
202 regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, WDT_TIMER_SELECT_VAL);
205 init_counter(dev, CNTR_ID_RETRIGGER, CNTR_CTRL_MODE_ONESHOT, 0);
206 set_counter_value(dev, CNTR_ID_RETRIGGER, 0);
209 init_counter(dev, CNTR_ID_WDOG, CNTR_CTRL_MODE_HWSIG,
211 set_counter_value(dev, CNTR_ID_WDOG, dev->timeout);
214 counter_enable(dev, CNTR_ID_WDOG);
217 counter_enable(dev, CNTR_ID_RETRIGGER);
224 struct armada_37xx_watchdog *dev = watchdog_get_drvdata(wdt);
226 counter_disable(dev, CNTR_ID_WDOG);
227 counter_disable(dev, CNTR_ID_RETRIGGER);
228 regmap_write(dev->cpu_misc, WDT_TIMER_SELECT, 0);
254 struct armada_37xx_watchdog *dev;
259 dev = devm_kzalloc(&pdev->dev, sizeof(struct armada_37xx_watchdog),
261 if (!dev)
264 dev->wdt.info = &armada_37xx_wdt_info;
265 dev->wdt.ops = &armada_37xx_wdt_ops;
267 regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
271 dev->cpu_misc = regmap;
276 dev->reg = devm_ioremap(&pdev->dev, res->start, resource_size(res));
277 if (!dev->reg)
281 dev->clk = devm_clk_get(&pdev->dev, NULL);
282 if (IS_ERR(dev->clk))
283 return PTR_ERR(dev->clk);
285 ret = clk_prepare_enable(dev->clk);
288 ret = devm_add_action_or_reset(&pdev->dev,
289 armada_clk_disable_unprepare, dev->clk);
293 dev->clk_rate = clk_get_rate(dev->clk);
294 if (!dev->clk_rate)
302 dev->wdt.min_timeout = 1;
303 dev->wdt.max_timeout = UINT_MAX;
304 dev->wdt.parent = &pdev->dev;
307 dev->wdt.timeout = WATCHDOG_TIMEOUT;
308 watchdog_init_timeout(&dev->wdt, timeout, &pdev->dev);
310 platform_set_drvdata(pdev, &dev->wdt);
311 watchdog_set_drvdata(&dev->wdt, dev);
313 armada_37xx_wdt_set_timeout(&dev->wdt, dev->wdt.timeout);
315 if (armada_37xx_wdt_is_running(dev))
316 set_bit(WDOG_HW_RUNNING, &dev->wdt.status);
318 watchdog_set_nowayout(&dev->wdt, nowayout);
319 watchdog_stop_on_reboot(&dev->wdt);
320 ret = devm_watchdog_register_device(&pdev->dev, &dev->wdt);
324 dev_info(&pdev->dev, "Initial timeout %d sec%s\n",
325 dev->wdt.timeout, nowayout ? ", nowayout" : "");
330 static int __maybe_unused armada_37xx_wdt_suspend(struct device *dev)
332 struct watchdog_device *wdt = dev_get_drvdata(dev);
337 static int __maybe_unused armada_37xx_wdt_resume(struct device *dev)
339 struct watchdog_device *wdt = dev_get_drvdata(dev);