Lines Matching refs:hdq_data
54 struct hdq_data {
68 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
70 return __raw_readl(hdq_data->hdq_base + offset);
73 static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
75 __raw_writel(val, hdq_data->hdq_base + offset);
78 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
81 u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask)
83 __raw_writel(new_val, hdq_data->hdq_base + offset);
94 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
102 while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
110 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
123 static u8 hdq_reset_irqstatus(struct hdq_data *hdq_data, u8 bits)
128 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
129 status = hdq_data->hdq_irqstatus;
131 hdq_data->hdq_irqstatus &= ~bits;
132 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
138 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
143 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
149 if (hdq_data->hdq_irqstatus)
150 dev_err(hdq_data->dev, "TX irqstatus not cleared (%02x)\n",
151 hdq_data->hdq_irqstatus);
155 hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
158 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
162 (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TXCOMPLETE),
164 *status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE);
166 dev_dbg(hdq_data->dev, "TX wait elapsed\n");
173 dev_dbg(hdq_data->dev, "timeout waiting for"
180 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
184 dev_dbg(hdq_data->dev, "timeout waiting GO bit"
189 mutex_unlock(&hdq_data->hdq_mutex);
197 struct hdq_data *hdq_data = _hdq;
200 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
201 hdq_data->hdq_irqstatus |= hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
202 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
203 dev_dbg(hdq_data->dev, "hdq_isr: %x\n", hdq_data->hdq_irqstatus);
205 if (hdq_data->hdq_irqstatus &
238 static int omap_hdq_break(struct hdq_data *hdq_data)
243 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
245 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
250 if (hdq_data->hdq_irqstatus)
251 dev_err(hdq_data->dev, "break irqstatus not cleared (%02x)\n",
252 hdq_data->hdq_irqstatus);
255 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
262 (hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_TIMEOUT),
264 tmp_status = hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TIMEOUT);
266 dev_dbg(hdq_data->dev, "break wait elapsed\n");
273 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x\n",
283 if (!(hdq_reg_in(hdq_data, OMAP_HDQ_CTRL_STATUS) &
285 dev_dbg(hdq_data->dev, "Presence bit not set\n");
294 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
299 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
303 mutex_unlock(&hdq_data->hdq_mutex);
308 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
313 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
319 if (pm_runtime_suspended(hdq_data->dev)) {
324 if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
325 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
332 (hdq_data->hdq_irqstatus
336 status = hdq_reset_irqstatus(hdq_data,
339 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
344 dev_dbg(hdq_data->dev, "timeout waiting for"
350 hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
353 *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
355 mutex_unlock(&hdq_data->hdq_mutex);
370 struct hdq_data *hdq_data = _hdq;
375 err = pm_runtime_get_sync(hdq_data->dev);
377 pm_runtime_put_noidle(hdq_data->dev);
382 err = mutex_lock_interruptible(&hdq_data->hdq_mutex);
384 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
392 (hdq_data->hdq_irqstatus
396 hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
399 dev_dbg(hdq_data->dev, "RX wait elapsed\n");
408 (hdq_data->hdq_irqstatus
412 hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_RXCOMPLETE);
415 dev_dbg(hdq_data->dev, "RX wait elapsed\n");
437 (hdq_data->hdq_irqstatus
441 hdq_reset_irqstatus(hdq_data, OMAP_HDQ_INT_STATUS_TXCOMPLETE);
444 dev_dbg(hdq_data->dev, "TX wait elapsed\n");
452 mutex_unlock(&hdq_data->hdq_mutex);
454 pm_runtime_mark_last_busy(hdq_data->dev);
455 pm_runtime_put_autosuspend(hdq_data->dev);
463 struct hdq_data *hdq_data = _hdq;
466 err = pm_runtime_get_sync(hdq_data->dev);
468 pm_runtime_put_noidle(hdq_data->dev);
473 omap_hdq_break(hdq_data);
475 pm_runtime_mark_last_busy(hdq_data->dev);
476 pm_runtime_put_autosuspend(hdq_data->dev);
484 struct hdq_data *hdq_data = _hdq;
488 ret = pm_runtime_get_sync(hdq_data->dev);
490 pm_runtime_put_noidle(hdq_data->dev);
495 ret = hdq_read_byte(hdq_data, &val);
499 pm_runtime_mark_last_busy(hdq_data->dev);
500 pm_runtime_put_autosuspend(hdq_data->dev);
508 struct hdq_data *hdq_data = _hdq;
512 ret = pm_runtime_get_sync(hdq_data->dev);
514 pm_runtime_put_noidle(hdq_data->dev);
525 omap_hdq_break(hdq_data);
527 ret = hdq_write_byte(hdq_data, byte, &status);
529 dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
534 pm_runtime_mark_last_busy(hdq_data->dev);
535 pm_runtime_put_autosuspend(hdq_data->dev);
546 struct hdq_data *hdq_data = dev_get_drvdata(dev);
548 hdq_reg_out(hdq_data, 0, hdq_data->mode);
549 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
556 struct hdq_data *hdq_data = dev_get_drvdata(dev);
559 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
562 hdq_data->mode);
563 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
576 struct hdq_data *hdq_data;
581 hdq_data = devm_kzalloc(dev, sizeof(*hdq_data), GFP_KERNEL);
582 if (!hdq_data) {
587 hdq_data->dev = dev;
588 platform_set_drvdata(pdev, hdq_data);
590 hdq_data->hdq_base = devm_platform_ioremap_resource(pdev, 0);
591 if (IS_ERR(hdq_data->hdq_base))
592 return PTR_ERR(hdq_data->hdq_base);
594 mutex_init(&hdq_data->hdq_mutex);
598 hdq_data->mode = 0;
601 hdq_data->mode = 1;
615 rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
619 spin_lock_init(&hdq_data->hdq_spinlock);
628 ret = devm_request_irq(dev, irq, hdq_isr, 0, "omap_hdq", hdq_data);
634 omap_hdq_break(hdq_data);
639 omap_w1_master.data = hdq_data;