Lines Matching refs:ds1wm_data
96 struct ds1wm_data {
116 static inline void ds1wm_write_register(struct ds1wm_data *ds1wm_data, u32 reg,
119 if (ds1wm_data->is_hw_big_endian) {
120 switch (ds1wm_data->bus_shift) {
122 iowrite8(val, ds1wm_data->map + (reg << 0));
125 iowrite16be((u16)val, ds1wm_data->map + (reg << 1));
128 iowrite32be((u32)val, ds1wm_data->map + (reg << 2));
132 switch (ds1wm_data->bus_shift) {
134 iowrite8(val, ds1wm_data->map + (reg << 0));
137 iowrite16((u16)val, ds1wm_data->map + (reg << 1));
140 iowrite32((u32)val, ds1wm_data->map + (reg << 2));
146 static inline u8 ds1wm_read_register(struct ds1wm_data *ds1wm_data, u32 reg)
150 if (ds1wm_data->is_hw_big_endian) {
151 switch (ds1wm_data->bus_shift) {
153 val = ioread8(ds1wm_data->map + (reg << 0));
156 val = ioread16be(ds1wm_data->map + (reg << 1));
159 val = ioread32be(ds1wm_data->map + (reg << 2));
163 switch (ds1wm_data->bus_shift) {
165 val = ioread8(ds1wm_data->map + (reg << 0));
168 val = ioread16(ds1wm_data->map + (reg << 1));
171 val = ioread32(ds1wm_data->map + (reg << 2));
175 dev_dbg(&ds1wm_data->pdev->dev,
183 struct ds1wm_data *ds1wm_data = data;
185 u8 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
191 ds1wm_write_register(ds1wm_data,
192 DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
195 intr = ds1wm_read_register(ds1wm_data, DS1WM_INT);
197 ds1wm_data->slave_present = (intr & DS1WM_INT_PDR) ? 0 : 1;
199 if ((intr & DS1WM_INT_TSRE) && ds1wm_data->write_complete) {
201 complete(ds1wm_data->write_complete);
205 ds1wm_data->read_byte = ds1wm_read_register(ds1wm_data,
208 if (ds1wm_data->read_complete)
209 complete(ds1wm_data->read_complete);
211 if ((intr & DS1WM_INT_PD) && ds1wm_data->reset_complete) {
213 complete(ds1wm_data->reset_complete);
216 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, inten);
220 static int ds1wm_reset(struct ds1wm_data *ds1wm_data)
225 ds1wm_data->reset_complete = &reset_done;
228 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, DS1WM_INTEN_EPD |
229 ds1wm_data->int_en_reg_none);
231 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_1W_RESET);
234 ds1wm_data->reset_complete = NULL;
236 dev_err(&ds1wm_data->pdev->dev, "reset failed, timed out\n");
240 if (!ds1wm_data->slave_present) {
241 dev_dbg(&ds1wm_data->pdev->dev, "reset: no devices found\n");
245 if (ds1wm_data->reset_recover_delay)
246 msleep(ds1wm_data->reset_recover_delay);
251 static int ds1wm_write(struct ds1wm_data *ds1wm_data, u8 data)
255 ds1wm_data->write_complete = &write_done;
257 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
258 ds1wm_data->int_en_reg_none | DS1WM_INTEN_ETMT);
260 ds1wm_write_register(ds1wm_data, DS1WM_DATA, data);
264 ds1wm_data->write_complete = NULL;
266 dev_err(&ds1wm_data->pdev->dev, "write failed, timed out\n");
273 static u8 ds1wm_read(struct ds1wm_data *ds1wm_data, unsigned char write_data)
276 u8 intEnable = DS1WM_INTEN_ERBF | ds1wm_data->int_en_reg_none;
279 ds1wm_read_register(ds1wm_data, DS1WM_DATA);
281 ds1wm_data->read_complete = &read_done;
282 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN, intEnable);
284 ds1wm_write_register(ds1wm_data, DS1WM_DATA, write_data);
287 ds1wm_data->read_complete = NULL;
289 dev_err(&ds1wm_data->pdev->dev, "read failed, timed out\n");
290 ds1wm_data->read_error = -ETIMEDOUT;
293 ds1wm_data->read_error = 0;
294 return ds1wm_data->read_byte;
308 static void ds1wm_up(struct ds1wm_data *ds1wm_data)
311 struct device *dev = &ds1wm_data->pdev->dev;
314 if (ds1wm_data->cell->enable)
315 ds1wm_data->cell->enable(ds1wm_data->pdev);
325 ds1wm_write_register(ds1wm_data, DS1WM_CLKDIV, divisor);
330 ds1wm_reset(ds1wm_data);
333 static void ds1wm_down(struct ds1wm_data *ds1wm_data)
335 ds1wm_reset(ds1wm_data);
338 ds1wm_write_register(ds1wm_data, DS1WM_INT_EN,
339 ds1wm_data->int_en_reg_none);
341 if (ds1wm_data->cell->disable)
342 ds1wm_data->cell->disable(ds1wm_data->pdev);
350 struct ds1wm_data *ds1wm_data = data;
352 return ds1wm_read(ds1wm_data, 0xff);
357 struct ds1wm_data *ds1wm_data = data;
359 ds1wm_write(ds1wm_data, byte);
364 struct ds1wm_data *ds1wm_data = data;
366 ds1wm_reset(ds1wm_data);
374 struct ds1wm_data *ds1wm_data = data;
382 dev_dbg(&ds1wm_data->pdev->dev, "search begin\n");
386 dev_dbg(&ds1wm_data->pdev->dev,
392 if (ds1wm_reset(ds1wm_data)) {
394 dev_dbg(&ds1wm_data->pdev->dev,
399 dev_dbg(&ds1wm_data->pdev->dev,
401 ds1wm_write(ds1wm_data, search_type);
402 dev_dbg(&ds1wm_data->pdev->dev,
404 ds1wm_write_register(ds1wm_data, DS1WM_CMD, DS1WM_CMD_SRA);
405 dev_dbg(&ds1wm_data->pdev->dev,
423 resp = ds1wm_read(ds1wm_data, _r);
425 if (ds1wm_data->read_error) {
426 dev_err(&ds1wm_data->pdev->dev,
445 if (ds1wm_data->read_error) {
447 dev_err(&ds1wm_data->pdev->dev,
451 dev_dbg(&ds1wm_data->pdev->dev,
454 dev_dbg(&ds1wm_data->pdev->dev,
456 ds1wm_write_register(ds1wm_data, DS1WM_CMD, ~DS1WM_CMD_SRA);
457 dev_dbg(&ds1wm_data->pdev->dev,
459 ds1wm_reset(ds1wm_data);
462 dev_err(&ds1wm_data->pdev->dev,
468 dev_dbg(&ds1wm_data->pdev->dev,
472 dev_dbg(&ds1wm_data->pdev->dev,
481 dev_dbg(&ds1wm_data->pdev->dev,
492 dev_dbg(&ds1wm_data->pdev->dev,
508 struct ds1wm_data *ds1wm_data;
517 ds1wm_data = devm_kzalloc(&pdev->dev, sizeof(*ds1wm_data), GFP_KERNEL);
518 if (!ds1wm_data)
521 platform_set_drvdata(pdev, ds1wm_data);
526 ds1wm_data->map = devm_ioremap(&pdev->dev, res->start,
528 if (!ds1wm_data->map)
531 ds1wm_data->pdev = pdev;
532 ds1wm_data->cell = mfd_get_cell(pdev);
533 if (!ds1wm_data->cell)
541 dev_err(&ds1wm_data->pdev->dev,
543 ds1wm_data->bus_shift);
547 ds1wm_data->bus_shift = plat->bus_shift;
549 if ((8 << ds1wm_data->bus_shift) > resource_size(res)) {
550 dev_err(&ds1wm_data->pdev->dev,
553 8 << ds1wm_data->bus_shift);
557 ds1wm_data->is_hw_big_endian = plat->is_hw_big_endian;
562 ds1wm_data->irq = res->start;
563 ds1wm_data->int_en_reg_none = (plat->active_high ? DS1WM_INTEN_IAS : 0);
564 ds1wm_data->reset_recover_delay = plat->reset_recover_delay;
567 inten = ds1wm_read_register(ds1wm_data, DS1WM_INT_EN);
568 ds1wm_write_register(ds1wm_data,
569 DS1WM_INT_EN, ds1wm_data->int_en_reg_none);
572 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_RISING);
574 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_EDGE_FALLING);
576 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_HIGH);
578 irq_set_irq_type(ds1wm_data->irq, IRQ_TYPE_LEVEL_LOW);
580 ret = devm_request_irq(&pdev->dev, ds1wm_data->irq, ds1wm_isr,
581 IRQF_SHARED, "ds1wm", ds1wm_data);
583 dev_err(&ds1wm_data->pdev->dev,
585 ds1wm_data->irq,
591 ds1wm_up(ds1wm_data);
593 ds1wm_master.data = (void *)ds1wm_data;
599 dev_dbg(&ds1wm_data->pdev->dev,
604 ds1wm_data->bus_shift,
605 ds1wm_data->is_hw_big_endian);
609 ds1wm_down(ds1wm_data);
617 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
619 ds1wm_down(ds1wm_data);
626 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
628 ds1wm_up(ds1wm_data);
639 struct ds1wm_data *ds1wm_data = platform_get_drvdata(pdev);
642 ds1wm_down(ds1wm_data);