Lines Matching refs:ioread32be
127 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
148 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
149 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
150 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
154 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
155 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
175 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
176 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
177 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
255 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
256 stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
388 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
410 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
414 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
423 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
427 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
448 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
539 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
632 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
635 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
637 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
639 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
641 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
643 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
645 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
903 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1065 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1068 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1070 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1072 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1074 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1076 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1078 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1384 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1386 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1400 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1405 result = ioread32be(image->kern_base + offset);
1408 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1793 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1854 dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1878 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
2004 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
2005 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
2006 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2059 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2079 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2083 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2111 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2115 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2129 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2150 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2217 cbar = ioread32be(bridge->base + TSI148_CBAR);
2229 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2264 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2480 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2508 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2611 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)