Lines Matching refs:cycle
49 u32 cycle;
57 u32 cycle;
156 dma_addr_t buf_base, u32 aspace, u32 cycle)
213 bridge->slaves[i].cycle = cycle;
225 dma_addr_t *buf_base, u32 *aspace, u32 *cycle)
241 *cycle = bridge->slaves[i].cycle;
253 u32 aspace, u32 cycle, u32 dwidth)
321 bridge->masters[i].cycle = cycle;
340 u32 *aspace, u32 *cycle, u32 *dwidth)
353 *cycle = bridge->masters[i].cycle;
362 u32 *aspace, u32 *cycle, u32 *dwidth)
369 cycle, dwidth);
378 u32 aspace, u32 cycle)
402 /* First make sure that the cycle and address space match */
403 if ((lm_aspace == aspace) && (lm_cycle == cycle)) {
419 u32 aspace, u32 cycle)
433 if (cycle != bridge->slaves[i].cycle)
445 fake_lm_check(bridge, addr, aspace, cycle);
452 u32 aspace, u32 cycle)
463 if (cycle != bridge->slaves[i].cycle)
478 fake_lm_check(bridge, addr, aspace, cycle);
485 u32 aspace, u32 cycle)
496 if (cycle != bridge->slaves[i].cycle)
511 fake_lm_check(bridge, addr, aspace, cycle);
520 u32 aspace, cycle, dwidth;
536 cycle = priv->masters[i].cycle;
545 * cycle configured for the transfer is used and splits it
547 * overhead of needlessly forcing small transfers for the entire cycle.
550 *(u8 *)buf = fake_vmeread8(priv, addr, aspace, cycle);
559 addr + done, aspace, cycle);
564 addr + done, aspace, cycle);
574 aspace, cycle);
581 aspace, cycle);
588 aspace, cycle);
597 aspace, cycle);
603 cycle);
617 u32 aspace, u32 cycle)
627 if (cycle != bridge->slaves[i].cycle)
642 fake_lm_check(bridge, addr, aspace, cycle);
648 u32 aspace, u32 cycle)
658 if (cycle != bridge->slaves[i].cycle)
673 fake_lm_check(bridge, addr, aspace, cycle);
679 u32 aspace, u32 cycle)
689 if (cycle != bridge->slaves[i].cycle)
704 fake_lm_check(bridge, addr, aspace, cycle);
712 u32 aspace, cycle, dwidth;
729 cycle = bridge->masters[i].cycle;
738 fake_vmewrite8(bridge, (u8 *)buf, addr, aspace, cycle);
748 addr + done, aspace, cycle);
753 addr + done, aspace, cycle);
763 addr + done, aspace, cycle);
770 addr + done, aspace, cycle);
777 aspace, cycle);
786 addr + done, aspace, cycle);
793 cycle);
806 * Perform an RMW cycle on the VME bus.
815 u32 aspace, cycle;
826 cycle = bridge->masters[i].cycle;
832 tmp = fake_vmeread32(bridge, base + offset, aspace, cycle);
840 fake_vmewrite32(bridge, &tmp, base + offset, aspace, cycle);
857 u32 aspace, u32 cycle)
892 bridge->lm_cycle = cycle;
903 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
913 *cycle = bridge->lm_cycle;