Lines Matching defs:aspace
48 u32 aspace;
56 u32 aspace;
156 dma_addr_t buf_base, u32 aspace, u32 cycle)
168 switch (aspace) {
212 bridge->slaves[i].aspace = aspace;
225 dma_addr_t *buf_base, u32 *aspace, u32 *cycle)
240 *aspace = bridge->slaves[i].aspace;
253 u32 aspace, u32 cycle, u32 dwidth)
296 switch (aspace) {
320 bridge->masters[i].aspace = aspace;
340 u32 *aspace, u32 *cycle, u32 *dwidth)
352 *aspace = bridge->masters[i].aspace;
362 u32 *aspace, u32 *cycle, u32 *dwidth)
368 retval = __fake_master_get(image, enabled, vme_base, size, aspace,
378 u32 aspace, u32 cycle)
403 if ((lm_aspace == aspace) && (lm_cycle == cycle)) {
419 u32 aspace, u32 cycle)
430 if (aspace != bridge->slaves[i].aspace)
445 fake_lm_check(bridge, addr, aspace, cycle);
452 u32 aspace, u32 cycle)
460 if (aspace != bridge->slaves[i].aspace)
478 fake_lm_check(bridge, addr, aspace, cycle);
485 u32 aspace, u32 cycle)
493 if (aspace != bridge->slaves[i].aspace)
511 fake_lm_check(bridge, addr, aspace, cycle);
520 u32 aspace, cycle, dwidth;
535 aspace = priv->masters[i].aspace;
550 *(u8 *)buf = fake_vmeread8(priv, addr, aspace, cycle);
559 addr + done, aspace, cycle);
564 addr + done, aspace, cycle);
574 aspace, cycle);
581 aspace, cycle);
588 aspace, cycle);
597 aspace, cycle);
602 *(u8 *)(buf + done) = fake_vmeread8(priv, addr + done, aspace,
617 u32 aspace, u32 cycle)
624 if (aspace != bridge->slaves[i].aspace)
642 fake_lm_check(bridge, addr, aspace, cycle);
648 u32 aspace, u32 cycle)
655 if (aspace != bridge->slaves[i].aspace)
673 fake_lm_check(bridge, addr, aspace, cycle);
679 u32 aspace, u32 cycle)
686 if (aspace != bridge->slaves[i].aspace)
704 fake_lm_check(bridge, addr, aspace, cycle);
712 u32 aspace, cycle, dwidth;
728 aspace = bridge->masters[i].aspace;
738 fake_vmewrite8(bridge, (u8 *)buf, addr, aspace, cycle);
748 addr + done, aspace, cycle);
753 addr + done, aspace, cycle);
763 addr + done, aspace, cycle);
770 addr + done, aspace, cycle);
777 aspace, cycle);
786 addr + done, aspace, cycle);
792 fake_vmewrite8(bridge, (u8 *)(buf + done), addr + done, aspace,
815 u32 aspace, cycle;
825 aspace = bridge->masters[i].aspace;
832 tmp = fake_vmeread32(bridge, base + offset, aspace, cycle);
840 fake_vmewrite32(bridge, &tmp, base + offset, aspace, cycle);
857 u32 aspace, u32 cycle)
878 switch (aspace) {
891 bridge->lm_aspace = aspace;
903 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
912 *aspace = bridge->lm_aspace;