Lines Matching refs:entry
511 dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n");
1021 struct ca91cx42_dma_entry *entry, *prev;
1031 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1032 if (!entry) {
1038 if ((unsigned long)&entry->descriptor & CA91CX42_DCPP_M) {
1040 "required: %p\n", &entry->descriptor);
1045 memset(&entry->descriptor, 0, sizeof(entry->descriptor));
1048 entry->descriptor.dctl |= CA91CX42_DCTL_L2V;
1085 entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT;
1090 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8;
1093 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16;
1096 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32;
1099 entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64;
1109 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16;
1112 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24;
1115 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32;
1118 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1;
1121 entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2;
1130 entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR;
1132 entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM;
1134 entry->descriptor.dtbc = count;
1135 entry->descriptor.dla = pci_attr->address;
1136 entry->descriptor.dva = vme_attr->address;
1137 entry->descriptor.dcpp = CA91CX42_DCPP_NULL;
1140 list_add_tail(&entry->list, &list->entries);
1143 if (entry->list.prev != &list->entries) {
1144 prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry,
1147 desc_ptr = virt_to_bus(&entry->descriptor);
1157 kfree(entry);
1180 struct ca91cx42_dma_entry *entry;
1208 entry = list_first_entry(&list->entries, struct ca91cx42_dma_entry,
1211 bus_addr = virt_to_bus(&entry->descriptor);
1274 struct ca91cx42_dma_entry *entry;
1276 /* detach and free each entry */
1279 entry = list_entry(pos, struct ca91cx42_dma_entry, list);
1280 kfree(entry);