Lines Matching defs:temp_ctl
338 unsigned int temp_ctl = 0;
404 temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
405 temp_ctl &= ~CA91CX42_VSI_CTL_EN;
406 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
414 temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M;
415 temp_ctl |= addr;
418 temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M);
420 temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR;
422 temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV;
424 temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM;
426 temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA;
429 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
432 temp_ctl |= CA91CX42_VSI_CTL_EN;
434 iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]);
595 unsigned int temp_ctl = 0;
650 temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
651 temp_ctl &= ~CA91CX42_LSI_CTL_EN;
652 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
655 temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M;
657 temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT;
659 temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT;
662 temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M;
665 temp_ctl |= CA91CX42_LSI_CTL_VDW_D8;
668 temp_ctl |= CA91CX42_LSI_CTL_VDW_D16;
671 temp_ctl |= CA91CX42_LSI_CTL_VDW_D32;
674 temp_ctl |= CA91CX42_LSI_CTL_VDW_D64;
685 temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M;
688 temp_ctl |= CA91CX42_LSI_CTL_VAS_A16;
691 temp_ctl |= CA91CX42_LSI_CTL_VAS_A24;
694 temp_ctl |= CA91CX42_LSI_CTL_VAS_A32;
697 temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR;
700 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1;
703 temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2;
716 temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M);
718 temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR;
720 temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM;
728 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);
731 temp_ctl |= CA91CX42_LSI_CTL_EN;
733 iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]);