Lines Matching defs:lm_ctl
1296 u32 temp_base, lm_ctl = 0;
1326 lm_ctl |= CA91CX42_LM_CTL_AS_A16;
1329 lm_ctl |= CA91CX42_LM_CTL_AS_A24;
1332 lm_ctl |= CA91CX42_LM_CTL_AS_A32;
1342 lm_ctl |= CA91CX42_LM_CTL_SUPR;
1344 lm_ctl |= CA91CX42_LM_CTL_NPRIV;
1346 lm_ctl |= CA91CX42_LM_CTL_PGM;
1348 lm_ctl |= CA91CX42_LM_CTL_DATA;
1351 iowrite32(lm_ctl, bridge->base + LM_CTL);
1364 u32 lm_ctl, enabled = 0;
1372 lm_ctl = ioread32(bridge->base + LM_CTL);
1374 if (lm_ctl & CA91CX42_LM_CTL_EN)
1377 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16)
1379 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24)
1381 if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32)
1385 if (lm_ctl & CA91CX42_LM_CTL_SUPR)
1387 if (lm_ctl & CA91CX42_LM_CTL_NPRIV)
1389 if (lm_ctl & CA91CX42_LM_CTL_PGM)
1391 if (lm_ctl & CA91CX42_LM_CTL_DATA)
1407 u32 lm_ctl, tmp;
1417 lm_ctl = ioread32(bridge->base + LM_CTL);
1418 if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) {
1441 if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) {
1442 lm_ctl |= CA91CX42_LM_CTL_EN;
1443 iowrite32(lm_ctl, bridge->base + LM_CTL);