Lines Matching defs:ctl
428 /* Write ctl reg without enable */
443 unsigned int i, granularity = 0, ctl = 0;
457 ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]);
470 if (ctl & CA91CX42_VSI_CTL_EN)
473 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16)
475 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24)
477 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32)
479 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1)
481 if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2)
484 if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR)
486 if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV)
488 if (ctl & CA91CX42_VSI_CTL_PGM_PGM)
490 if (ctl & CA91CX42_VSI_CTL_PGM_DATA)
727 /* Write ctl reg without enable */
750 unsigned int i, ctl;
758 ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]);
772 if (ctl & CA91CX42_LSI_CTL_EN)
776 switch (ctl & CA91CX42_LSI_CTL_VAS_M) {
799 if (ctl & CA91CX42_LSI_CTL_VCT_BLT)
804 if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR)
809 if (ctl & CA91CX42_LSI_CTL_PGM_PGM)
815 switch (ctl & CA91CX42_LSI_CTL_VDW_M) {