Lines Matching refs:remapped_regs
65 static void __iomem *remapped_regs;
115 param = readl(remapped_regs + regs);
129 writel(param, remapped_regs + regs);
269 status.val = readl(remapped_regs + mmRBBM_STATUS);
284 status.val = readl(remapped_regs + mmRBBM_STATUS);
302 writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET);
303 writel(par->xres, remapped_regs + mmDST_PITCH);
304 writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET);
305 writel(par->xres, remapped_regs + mmSRC_PITCH);
308 writel(0, remapped_regs + mmSC_TOP_LEFT);
309 writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT);
310 writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT);
320 writel(dp_cntl.val, remapped_regs + mmDP_CNTL);
337 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
346 writel(dp_datatype.val, remapped_regs + mmDP_DATATYPE);
352 writel(dp_mix.val, remapped_regs + mmDP_MIX);
368 gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
372 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
373 writel(rect->color, remapped_regs + mmDP_BRUSH_FRGD_CLR);
376 writel((rect->dy << 16) | (rect->dx & 0xffff), remapped_regs + mmDST_Y_X);
378 remapped_regs + mmDST_WIDTH_HEIGHT);
396 gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
400 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
403 writel((sy << 16) | (sx & 0xffff), remapped_regs + mmSRC_Y_X);
404 writel((dy << 16) | (dx & 0xffff), remapped_regs + mmDST_Y_X);
405 writel((w << 16) | (h & 0xffff), remapped_regs + mmDST_WIDTH_HEIGHT);
658 remapped_regs = ioremap(mem->start+W100_REG_BASE, W100_REG_LEN);
659 if (remapped_regs == NULL)
664 chip_id = readl(remapped_regs + mmCHIP_ID);
777 if (remapped_regs != NULL) {
778 iounmap(remapped_regs);
779 remapped_regs = NULL;
805 iounmap(remapped_regs);
806 remapped_regs = NULL;
837 writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL);
848 writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL);
856 value = readl(remapped_regs + mmGPIO_DATA);
858 value = readl(remapped_regs + mmGPIO_DATA2);
866 writel(value, remapped_regs + mmGPIO_DATA);
868 writel(value, remapped_regs + mmGPIO_DATA2);
894 writel(0x31, remapped_regs + mmSCRATCH_UMSK);
896 readl(remapped_regs + mmSCRATCH_UMSK);
897 writel(0x30, remapped_regs + mmSCRATCH_UMSK);
901 writel((u32)(cif_io.val), remapped_regs + mmCIF_IO);
903 cif_write_dbg.val = readl(remapped_regs + mmCIF_WRITE_DBG);
907 writel((u32) (cif_write_dbg.val), remapped_regs + mmCIF_WRITE_DBG);
909 cif_read_dbg.val = readl(remapped_regs + mmCIF_READ_DBG);
911 writel((u32) (cif_read_dbg.val), remapped_regs + mmCIF_READ_DBG);
913 cif_cntl.val = readl(remapped_regs + mmCIF_CNTL);
919 writel((u32) (cif_cntl.val), remapped_regs + mmCIF_CNTL);
941 writel((u32) (cfgreg_base.val), remapped_regs + mmCFGREG_BASE);
945 writel((u32) (wrap_start_dir.val), remapped_regs + mmWRAP_START_DIR);
949 writel((u32) (wrap_top_dir.val), remapped_regs + mmWRAP_TOP_DIR);
951 writel((u32) 0x2440, remapped_regs + mmRBBM_CNTL);
954 temp32 = readl(remapped_regs + mmDISP_DEBUG2);
957 writel(temp32, remapped_regs + mmDISP_DEBUG2);
961 writel(gpio->init_data1, remapped_regs + mmGPIO_DATA);
962 writel(gpio->init_data2, remapped_regs + mmGPIO_DATA2);
963 writel(gpio->gpio_dir1, remapped_regs + mmGPIO_CNTL1);
964 writel(gpio->gpio_oe1, remapped_regs + mmGPIO_CNTL2);
965 writel(gpio->gpio_dir2, remapped_regs + mmGPIO_CNTL3);
966 writel(gpio->gpio_oe2, remapped_regs + mmGPIO_CNTL4);
1052 writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
1055 writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
1059 writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
1065 clk_test_cntl.val = readl(remapped_regs + mmCLK_TEST_CNTL);
1067 writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
1094 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1100 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1140 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1146 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1150 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1168 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
1173 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
1179 writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV);
1182 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
1190 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
1219 writel((u32) (w100_pwr_state.clk_pin_cntl.val), remapped_regs + mmCLK_PIN_CNTL);
1239 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
1244 writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL);
1251 writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV);
1271 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1282 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
1301 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
1320 writel(active_h_disp.val, remapped_regs + mmACTIVE_H_DISP);
1325 writel(active_v_disp.val, remapped_regs + mmACTIVE_V_DISP);
1330 writel(graphic_h_disp.val, remapped_regs + mmGRAPHIC_H_DISP);
1335 writel(graphic_v_disp.val, remapped_regs + mmGRAPHIC_V_DISP);
1340 writel(crtc_total.val, remapped_regs + mmCRTC_TOTAL);
1342 writel(mode->crtc_ss, remapped_regs + mmCRTC_SS);
1343 writel(mode->crtc_ls, remapped_regs + mmCRTC_LS);
1344 writel(mode->crtc_gs, remapped_regs + mmCRTC_GS);
1345 writel(mode->crtc_vpos_gs, remapped_regs + mmCRTC_VPOS_GS);
1346 writel(mode->crtc_rev, remapped_regs + mmCRTC_REV);
1347 writel(mode->crtc_dclk, remapped_regs + mmCRTC_DCLK);
1348 writel(mode->crtc_gclk, remapped_regs + mmCRTC_GCLK);
1349 writel(mode->crtc_goe, remapped_regs + mmCRTC_GOE);
1350 writel(mode->crtc_ps1_active, remapped_regs + mmCRTC_PS1_ACTIVE);
1352 writel(regs->lcd_format, remapped_regs + mmLCD_FORMAT);
1353 writel(regs->lcdd_cntl1, remapped_regs + mmLCDD_CNTL1);
1354 writel(regs->lcdd_cntl2, remapped_regs + mmLCDD_CNTL2);
1355 writel(regs->genlcd_cntl1, remapped_regs + mmGENLCD_CNTL1);
1356 writel(regs->genlcd_cntl2, remapped_regs + mmGENLCD_CNTL2);
1357 writel(regs->genlcd_cntl3, remapped_regs + mmGENLCD_CNTL3);
1359 writel(0x00000000, remapped_regs + mmCRTC_FRAME);
1360 writel(0x00000000, remapped_regs + mmCRTC_FRAME_VPOS);
1361 writel(0x00000000, remapped_regs + mmCRTC_DEFAULT_COUNT);
1362 writel(0x0000FF00, remapped_regs + mmLCD_BACKGROUND_COLOR);
1365 temp32 = readl(remapped_regs + mmDISP_DEBUG2);
1367 writel(temp32, remapped_regs + mmDISP_DEBUG2);
1384 writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION);
1390 writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION);
1395 writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION);
1400 writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION);
1402 writel(0x00007800, remapped_regs + mmMC_BIST_CTRL);
1403 writel(mem->ext_cntl, remapped_regs + mmMEM_EXT_CNTL);
1404 writel(0x00200021, remapped_regs + mmMEM_SDRAM_MODE_REG);
1406 writel(0x80200021, remapped_regs + mmMEM_SDRAM_MODE_REG);
1408 writel(mem->sdram_mode_reg, remapped_regs + mmMEM_SDRAM_MODE_REG);
1410 writel(mem->ext_timing_cntl, remapped_regs + mmMEM_EXT_TIMING_CNTL);
1411 writel(mem->io_cntl, remapped_regs + mmMEM_IO_CNTL);
1413 writel(bm_mem->ext_mem_bw, remapped_regs + mmBM_EXT_MEM_BANDWIDTH);
1414 writel(bm_mem->offset, remapped_regs + mmBM_OFFSET);
1415 writel(bm_mem->ext_timing_ctl, remapped_regs + mmBM_MEM_EXT_TIMING_CNTL);
1416 writel(bm_mem->ext_cntl, remapped_regs + mmBM_MEM_EXT_CNTL);
1417 writel(bm_mem->mode_reg, remapped_regs + mmBM_MEM_MODE_REG);
1418 writel(bm_mem->io_cntl, remapped_regs + mmBM_MEM_IO_CNTL);
1419 writel(bm_mem->config, remapped_regs + mmBM_CONFIG);
1504 writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL);
1506 writel(graphic_ctrl.val, remapped_regs + mmGRAPHIC_CTRL);
1507 writel(W100_FB_BASE + ((offset * BITS_PER_PIXEL/8)&~0x03UL), remapped_regs + mmGRAPHIC_OFFSET);
1508 writel((par->xres*BITS_PER_PIXEL/8), remapped_regs + mmGRAPHIC_PITCH);
1529 crtc_ss.val = readl(remapped_regs + mmCRTC_SS);
1540 writel(0x7FFF8000, remapped_regs + mmMC_EXT_MEM_LOCATION);
1541 writel(0x00FF0000, remapped_regs + mmMC_PERF_MON_CNTL);
1543 val = readl(remapped_regs + mmMEM_EXT_TIMING_CNTL);
1546 writel(val, remapped_regs + mmMEM_EXT_TIMING_CNTL);
1548 val = readl(remapped_regs + mmMEM_EXT_CNTL);
1551 writel(val, remapped_regs + mmMEM_EXT_CNTL);
1557 val = readl(remapped_regs + mmMEM_EXT_CNTL);
1559 writel(val, remapped_regs + mmMEM_EXT_CNTL);
1562 val = readl(remapped_regs + mmMEM_EXT_CNTL);
1564 writel(val, remapped_regs + mmMEM_EXT_CNTL);
1566 writel(0x00000000, remapped_regs + mmSCLK_CNTL);
1567 writel(0x000000BF, remapped_regs + mmCLK_PIN_CNTL);
1568 writel(0x00000015, remapped_regs + mmPWRMGT_CNTL);
1572 val = readl(remapped_regs + mmPLL_CNTL);
1574 writel(val, remapped_regs + mmPLL_CNTL);
1576 writel(0x00000000, remapped_regs + mmLCDD_CNTL1);
1577 writel(0x00000000, remapped_regs + mmLCDD_CNTL2);
1578 writel(0x00000000, remapped_regs + mmGENLCD_CNTL1);
1579 writel(0x00000000, remapped_regs + mmGENLCD_CNTL2);
1580 writel(0x00000000, remapped_regs + mmGENLCD_CNTL3);
1582 val = readl(remapped_regs + mmMEM_EXT_CNTL);
1585 writel(val, remapped_regs + mmMEM_EXT_CNTL);
1587 writel(0x0000001d, remapped_regs + mmPWRMGT_CNTL);
1596 tmp = readl(remapped_regs + mmACTIVE_V_DISP);
1599 writel((tmp >> 16) & 0x3ff, remapped_regs + mmDISP_INT_CNTL);
1602 tmp = readl(remapped_regs + mmGEN_INT_CNTL);
1605 writel(tmp, remapped_regs + mmGEN_INT_CNTL);
1608 writel(0x00000002, remapped_regs + mmGEN_INT_STATUS);
1611 writel((tmp | 0x00000002), remapped_regs + mmGEN_INT_CNTL);
1614 writel(0x00000002, remapped_regs + mmGEN_INT_STATUS);
1617 if (readl(remapped_regs + mmGEN_INT_STATUS) & 0x00000002)
1624 writel(tmp, remapped_regs + mmGEN_INT_CNTL);
1627 writel(0x00000002, remapped_regs + mmGEN_INT_STATUS);