Lines Matching defs:w100_pwr_state
982 static struct power_state w100_pwr_state;
1079 w100_pwr_state.pll_cntl.f.pll_pwdn = 0x0; /* power down */
1080 w100_pwr_state.pll_cntl.f.pll_reset = 0x0; /* not reset */
1081 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x1; /* Hi-Z */
1082 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0; /* VCO gain = 0 */
1083 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0; /* VCO frequency range control = off */
1084 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0; /* current offset inside VCO = 0 */
1085 w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;
1093 w100_pwr_state.pll_cntl.f.pll_dactal = 0xd;
1094 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1099 w100_pwr_state.pll_cntl.f.pll_dactal = 0x7;
1100 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1106 if ((w100_pwr_state.pll_cntl.f.pll_vcofr == 0x0) &&
1107 ((w100_pwr_state.pll_cntl.f.pll_pvg == 0x7) ||
1108 (w100_pwr_state.pll_cntl.f.pll_ioffset == 0x0))) {
1110 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x1;
1111 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;
1112 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
1116 if ((w100_pwr_state.pll_cntl.f.pll_ioffset) < 0x3) {
1117 w100_pwr_state.pll_cntl.f.pll_ioffset += 0x1;
1118 } else if ((w100_pwr_state.pll_cntl.f.pll_pvg) < 0x7) {
1119 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
1120 w100_pwr_state.pll_cntl.f.pll_pvg += 0x1;
1139 w100_pwr_state.pll_cntl.f.pll_dactal = 0xa;
1140 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1145 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0; /* normal */
1146 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1149 w100_pwr_state.pll_cntl.f.pll_dactal = 0x0;
1150 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1164 if (w100_pwr_state.auto_mode == 1) /* auto mode */
1166 w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0; /* disable fast to normal */
1167 w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0; /* disable normal to fast */
1168 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
1172 w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL;
1173 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
1175 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M;
1176 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int;
1177 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac;
1178 w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll->lock_time;
1179 writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV);
1181 w100_pwr_state.pwrmgt_cntl.f.pwm_mode_req = 0;
1182 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
1186 if (w100_pwr_state.auto_mode == 1) /* auto mode */
1188 w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x1; /* reenable fast to normal */
1189 w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x1; /* reenable normal to fast */
1190 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
1213 w100_pwr_state.clk_pin_cntl.f.osc_en = 0x1;
1214 w100_pwr_state.clk_pin_cntl.f.osc_gain = 0x1f;
1215 w100_pwr_state.clk_pin_cntl.f.dont_use_xtalin = 0x0;
1216 w100_pwr_state.clk_pin_cntl.f.xtalin_pm_en = 0x0;
1217 w100_pwr_state.clk_pin_cntl.f.xtalin_dbl_en = par->mach->xtal_dbl ? 1 : 0;
1218 w100_pwr_state.clk_pin_cntl.f.cg_debug = 0x0;
1219 writel((u32) (w100_pwr_state.clk_pin_cntl.val), remapped_regs + mmCLK_PIN_CNTL);
1221 w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL;
1222 w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = 0x0; /* Pfast = 1 */
1223 w100_pwr_state.sclk_cntl.f.sclk_clkon_hys = 0x3;
1224 w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = 0x0; /* Pslow = 1 */
1225 w100_pwr_state.sclk_cntl.f.disp_cg_ok2switch_en = 0x0;
1226 w100_pwr_state.sclk_cntl.f.sclk_force_reg = 0x0; /* Dynamic */
1227 w100_pwr_state.sclk_cntl.f.sclk_force_disp = 0x0; /* Dynamic */
1228 w100_pwr_state.sclk_cntl.f.sclk_force_mc = 0x0; /* Dynamic */
1229 w100_pwr_state.sclk_cntl.f.sclk_force_extmc = 0x0; /* Dynamic */
1230 w100_pwr_state.sclk_cntl.f.sclk_force_cp = 0x0; /* Dynamic */
1231 w100_pwr_state.sclk_cntl.f.sclk_force_e2 = 0x0; /* Dynamic */
1232 w100_pwr_state.sclk_cntl.f.sclk_force_e3 = 0x0; /* Dynamic */
1233 w100_pwr_state.sclk_cntl.f.sclk_force_idct = 0x0; /* Dynamic */
1234 w100_pwr_state.sclk_cntl.f.sclk_force_bist = 0x0; /* Dynamic */
1235 w100_pwr_state.sclk_cntl.f.busy_extend_cp = 0x0;
1236 w100_pwr_state.sclk_cntl.f.busy_extend_e2 = 0x0;
1237 w100_pwr_state.sclk_cntl.f.busy_extend_e3 = 0x0;
1238 w100_pwr_state.sclk_cntl.f.busy_extend_idct = 0x0;
1239 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
1241 w100_pwr_state.pclk_cntl.f.pclk_src_sel = CLK_SRC_XTAL;
1242 w100_pwr_state.pclk_cntl.f.pclk_post_div = 0x1; /* P = 2 */
1243 w100_pwr_state.pclk_cntl.f.pclk_force_disp = 0x0; /* Dynamic */
1244 writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL);
1246 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = 0x0; /* M = 1 */
1247 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = 0x0; /* N = 1.0 */
1248 w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = 0x0;
1249 w100_pwr_state.pll_ref_fb_div.f.pll_reset_time = 0x5;
1250 w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = 0xff;
1251 writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV);
1253 w100_pwr_state.pll_cntl.f.pll_pwdn = 0x1;
1254 w100_pwr_state.pll_cntl.f.pll_reset = 0x1;
1255 w100_pwr_state.pll_cntl.f.pll_pm_en = 0x0;
1256 w100_pwr_state.pll_cntl.f.pll_mode = 0x0; /* uses VCO clock */
1257 w100_pwr_state.pll_cntl.f.pll_refclk_sel = 0x0;
1258 w100_pwr_state.pll_cntl.f.pll_fbclk_sel = 0x0;
1259 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0;
1260 w100_pwr_state.pll_cntl.f.pll_pcp = 0x4;
1261 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;
1262 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0;
1263 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
1264 w100_pwr_state.pll_cntl.f.pll_pecc_mode = 0x0;
1265 w100_pwr_state.pll_cntl.f.pll_pecc_scon = 0x0;
1266 w100_pwr_state.pll_cntl.f.pll_dactal = 0x0; /* Hi-Z */
1267 w100_pwr_state.pll_cntl.f.pll_cp_clip = 0x3;
1268 w100_pwr_state.pll_cntl.f.pll_conf = 0x2;
1269 w100_pwr_state.pll_cntl.f.pll_mbctrl = 0x2;
1270 w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;
1271 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1273 w100_pwr_state.pwrmgt_cntl.f.pwm_enable = 0x0;
1274 w100_pwr_state.pwrmgt_cntl.f.pwm_mode_req = 0x1; /* normal mode (0, 1, 3) */
1275 w100_pwr_state.pwrmgt_cntl.f.pwm_wakeup_cond = 0x0;
1276 w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0;
1277 w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0;
1278 w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_cond = 0x1; /* PM4,ENG */
1279 w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_cond = 0x1; /* PM4,ENG */
1280 w100_pwr_state.pwrmgt_cntl.f.pwm_idle_timer = 0xFF;
1281 w100_pwr_state.pwrmgt_cntl.f.pwm_busy_timer = 0xFF;
1282 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
1284 w100_pwr_state.auto_mode = 0; /* manual mode */
1298 w100_pwr_state.sclk_cntl.f.sclk_src_sel = mode->sysclk_src;
1299 w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = mode->sysclk_divider;
1300 w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = mode->sysclk_divider;
1301 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
1502 w100_pwr_state.pclk_cntl.f.pclk_src_sel = par->mode->pixclk_src;
1503 w100_pwr_state.pclk_cntl.f.pclk_post_div = divider;
1504 writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL);
1527 hsync /= (w100_pwr_state.pclk_cntl.f.pclk_post_div + 1);