Lines Matching defs:pll_cntl
974 union pll_cntl_u pll_cntl;
1079 w100_pwr_state.pll_cntl.f.pll_pwdn = 0x0; /* power down */
1080 w100_pwr_state.pll_cntl.f.pll_reset = 0x0; /* not reset */
1081 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x1; /* Hi-Z */
1082 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0; /* VCO gain = 0 */
1083 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0; /* VCO frequency range control = off */
1084 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0; /* current offset inside VCO = 0 */
1085 w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;
1093 w100_pwr_state.pll_cntl.f.pll_dactal = 0xd;
1094 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1099 w100_pwr_state.pll_cntl.f.pll_dactal = 0x7;
1100 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1106 if ((w100_pwr_state.pll_cntl.f.pll_vcofr == 0x0) &&
1107 ((w100_pwr_state.pll_cntl.f.pll_pvg == 0x7) ||
1108 (w100_pwr_state.pll_cntl.f.pll_ioffset == 0x0))) {
1110 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x1;
1111 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;
1112 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
1116 if ((w100_pwr_state.pll_cntl.f.pll_ioffset) < 0x3) {
1117 w100_pwr_state.pll_cntl.f.pll_ioffset += 0x1;
1118 } else if ((w100_pwr_state.pll_cntl.f.pll_pvg) < 0x7) {
1119 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
1120 w100_pwr_state.pll_cntl.f.pll_pvg += 0x1;
1139 w100_pwr_state.pll_cntl.f.pll_dactal = 0xa;
1140 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1145 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0; /* normal */
1146 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1149 w100_pwr_state.pll_cntl.f.pll_dactal = 0x0;
1150 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
1253 w100_pwr_state.pll_cntl.f.pll_pwdn = 0x1;
1254 w100_pwr_state.pll_cntl.f.pll_reset = 0x1;
1255 w100_pwr_state.pll_cntl.f.pll_pm_en = 0x0;
1256 w100_pwr_state.pll_cntl.f.pll_mode = 0x0; /* uses VCO clock */
1257 w100_pwr_state.pll_cntl.f.pll_refclk_sel = 0x0;
1258 w100_pwr_state.pll_cntl.f.pll_fbclk_sel = 0x0;
1259 w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0;
1260 w100_pwr_state.pll_cntl.f.pll_pcp = 0x4;
1261 w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;
1262 w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0;
1263 w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
1264 w100_pwr_state.pll_cntl.f.pll_pecc_mode = 0x0;
1265 w100_pwr_state.pll_cntl.f.pll_pecc_scon = 0x0;
1266 w100_pwr_state.pll_cntl.f.pll_dactal = 0x0; /* Hi-Z */
1267 w100_pwr_state.pll_cntl.f.pll_cp_clip = 0x3;
1268 w100_pwr_state.pll_cntl.f.pll_conf = 0x2;
1269 w100_pwr_state.pll_cntl.f.pll_mbctrl = 0x2;
1270 w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;
1271 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);