Lines Matching refs:vgabase
118 svga_tilecursor(par->state.vgabase, info, cursor);
264 regval = vga_r(par->state.vgabase, VGA_MIS_R);
265 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
268 vga_wseq(par->state.vgabase, 0x46, (n | (r << 6)));
269 vga_wseq(par->state.vgabase, 0x47, m);
274 svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02);
275 svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02);
285 void __iomem *vgabase = par->state.vgabase;
288 par->state.vgabase = vgabase;
420 svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01);
421 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
422 svga_wcrt_mask(par->state.vgabase, 0x47, 0x00, 0x01);
425 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
426 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
427 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
430 svga_set_default_gfx_regs(par->state.vgabase);
431 svga_set_default_atc_regs(par->state.vgabase);
432 svga_set_default_seq_regs(par->state.vgabase);
433 svga_set_default_crt_regs(par->state.vgabase);
434 svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF);
435 svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0);
437 svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value);
438 svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value);
441 svga_wcrt_mask(par->state.vgabase, 0x03, 0x00, 0x60);
442 svga_wcrt_mask(par->state.vgabase, 0x05, 0x00, 0x60);
445 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
447 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
449 svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus
450 svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus
451 svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold
452 vga_wseq(par->state.vgabase, 0x17, 0x1F); // FIFO depth
453 vga_wseq(par->state.vgabase, 0x18, 0x4E);
454 svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ?
456 vga_wcrt(par->state.vgabase, 0x32, 0x00);
457 vga_wcrt(par->state.vgabase, 0x34, 0x00);
458 vga_wcrt(par->state.vgabase, 0x6A, 0x80);
459 vga_wcrt(par->state.vgabase, 0x6A, 0xC0);
461 vga_wgfx(par->state.vgabase, 0x20, 0x00);
462 vga_wgfx(par->state.vgabase, 0x21, 0x00);
463 vga_wgfx(par->state.vgabase, 0x22, 0x00);
470 svga_set_textmode_vga_regs(par->state.vgabase);
471 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
472 svga_wcrt_mask(par->state.vgabase, 0x11, 0x60, 0x70);
476 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
477 svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE);
478 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
482 svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
483 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x70);
487 svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE);
491 svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE);
495 svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE);
503 svga_set_timings(par->state.vgabase, &vt8623_timing_regs, &(info->var), 1, 1,
512 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
513 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
514 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
582 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
583 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
587 svga_wcrt_mask(par->state.vgabase, 0x36, 0x00, 0x30);
588 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
592 svga_wcrt_mask(par->state.vgabase, 0x36, 0x10, 0x30);
593 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
597 svga_wcrt_mask(par->state.vgabase, 0x36, 0x20, 0x30);
598 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
602 svga_wcrt_mask(par->state.vgabase, 0x36, 0x30, 0x30);
603 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
628 svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, offset);
724 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
727 memsize1 = (vga_rseq(par->state.vgabase, 0x34) + 1) >> 1;
728 memsize2 = vga_rseq(par->state.vgabase, 0x39) << 2;