Lines Matching refs:data
42 static inline void cle266_set_primary_pll_encoded(u32 data)
45 via_write_reg(VIASR, 0x46, data & 0xFF);
46 via_write_reg(VIASR, 0x47, (data >> 8) & 0xFF);
50 static inline void k800_set_primary_pll_encoded(u32 data)
53 via_write_reg(VIASR, 0x44, data & 0xFF);
54 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
55 via_write_reg(VIASR, 0x46, (data >> 16) & 0xFF);
59 static inline void cle266_set_secondary_pll_encoded(u32 data)
62 via_write_reg(VIASR, 0x44, data & 0xFF);
63 via_write_reg(VIASR, 0x45, (data >> 8) & 0xFF);
67 static inline void k800_set_secondary_pll_encoded(u32 data)
70 via_write_reg(VIASR, 0x4A, data & 0xFF);
71 via_write_reg(VIASR, 0x4B, (data >> 8) & 0xFF);
72 via_write_reg(VIASR, 0x4C, (data >> 16) & 0xFF);
76 static inline void set_engine_pll_encoded(u32 data)
79 via_write_reg(VIASR, 0x47, data & 0xFF);
80 via_write_reg(VIASR, 0x48, (data >> 8) & 0xFF);
81 via_write_reg(VIASR, 0x49, (data >> 16) & 0xFF);
217 u8 data = 0;
221 data = 0x00;
224 data = 0x02;
227 data = 0x04; /* 0x06 should be the same */
230 data = 0x0A;
233 data = 0xC;
236 data = 0x0E;
241 data |= 1;
243 return data;
248 u8 data = set_clock_source_common(source, use_pll) << 4;
249 via_write_reg_mask(VIACR, 0x6C, data, 0xF0);
254 u8 data = set_clock_source_common(source, use_pll);
255 via_write_reg_mask(VIACR, 0x6C, data, 0x0F);