Lines Matching defs:par
267 static int vmlfb_get_gpu(struct vml_par *par)
271 par->gpu = pci_get_device(PCI_VENDOR_ID_INTEL, VML_DEVICE_GPU, NULL);
273 if (!par->gpu) {
280 if (pci_enable_device(par->gpu) < 0) {
281 pci_dev_put(par->gpu);
311 static int vmlfb_enable_mmio(struct vml_par *par)
315 par->vdc_mem_base = pci_resource_start(par->vdc, 0);
316 par->vdc_mem_size = pci_resource_len(par->vdc, 0);
317 if (!request_mem_region(par->vdc_mem_base, par->vdc_mem_size, "vmlfb")) {
322 par->vdc_mem = ioremap(par->vdc_mem_base, par->vdc_mem_size);
323 if (par->vdc_mem == NULL) {
330 par->gpu_mem_base = pci_resource_start(par->gpu, 0);
331 par->gpu_mem_size = pci_resource_len(par->gpu, 0);
332 if (!request_mem_region(par->gpu_mem_base, par->gpu_mem_size, "vmlfb")) {
337 par->gpu_mem = ioremap(par->gpu_mem_base, par->gpu_mem_size);
338 if (par->gpu_mem == NULL) {
347 release_mem_region(par->gpu_mem_base, par->gpu_mem_size);
349 iounmap(par->vdc_mem);
351 release_mem_region(par->vdc_mem_base, par->vdc_mem_size);
359 static void vmlfb_disable_mmio(struct vml_par *par)
361 iounmap(par->gpu_mem);
362 release_mem_region(par->gpu_mem_base, par->gpu_mem_size);
363 iounmap(par->vdc_mem);
364 release_mem_region(par->vdc_mem_base, par->vdc_mem_size);
371 static void vmlfb_release_devices(struct vml_par *par)
373 if (atomic_dec_and_test(&par->refcount)) {
374 pci_disable_device(par->gpu);
375 pci_disable_device(par->vdc);
387 struct vml_par *par;
392 par = vinfo->par;
397 vmlfb_disable_mmio(par);
398 vmlfb_release_devices(par);
400 kfree(par);
446 struct vml_par *par;
449 par = kzalloc(sizeof(*par), GFP_KERNEL);
450 if (par == NULL)
459 vinfo->par = par;
460 par->vdc = dev;
461 atomic_set(&par->refcount, 1);
465 if ((err = vmlfb_get_gpu(par)))
477 err = vmlfb_enable_mmio(par);
499 info->par = par;
536 vmlfb_disable_mmio(par);
538 vmlfb_release_devices(par);
542 kfree(par);
700 struct vml_par *par = vinfo->par;
703 VML_WRITE32(par, VML_RCOMPSTAT, 0);
704 while (!(VML_READ32(par, VML_RCOMPSTAT) & VML_MDVO_VDC_I_RCOMP)) ;
707 VML_WRITE32(par, VML_DSPCCNTR,
708 VML_READ32(par, VML_DSPCCNTR) & ~VML_GFX_ENABLE);
709 (void)VML_READ32(par, VML_DSPCCNTR);
714 VML_WRITE32(par, VML_PIPEACONF, 0);
715 (void)VML_READ32(par, VML_PIPEACONF);
723 struct vml_par *par = vinfo->par;
727 (unsigned)VML_READ32(par, VML_HTOTAL_A));
729 (unsigned)VML_READ32(par, VML_HBLANK_A));
731 (unsigned)VML_READ32(par, VML_HSYNC_A));
733 (unsigned)VML_READ32(par, VML_VTOTAL_A));
735 (unsigned)VML_READ32(par, VML_VBLANK_A));
737 (unsigned)VML_READ32(par, VML_VSYNC_A));
739 (unsigned)VML_READ32(par, VML_DSPCSTRIDE));
741 (unsigned)VML_READ32(par, VML_DSPCSIZE));
743 (unsigned)VML_READ32(par, VML_DSPCPOS));
745 (unsigned)VML_READ32(par, VML_DSPARB));
747 (unsigned)VML_READ32(par, VML_DSPCADDR));
749 (unsigned)VML_READ32(par, VML_BCLRPAT_A));
751 (unsigned)VML_READ32(par, VML_CANVSCLR_A));
753 (unsigned)VML_READ32(par, VML_PIPEASRC));
755 (unsigned)VML_READ32(par, VML_PIPEACONF));
757 (unsigned)VML_READ32(par, VML_DSPCCNTR));
759 (unsigned)VML_READ32(par, VML_RCOMPSTAT));
766 struct vml_par *par = vinfo->par;
831 VML_WRITE32(par, VML_HTOTAL_A, ((htotal - 1) << 16) | (hactive - 1));
832 VML_WRITE32(par, VML_HBLANK_A,
834 VML_WRITE32(par, VML_HSYNC_A,
836 VML_WRITE32(par, VML_VTOTAL_A, ((vtotal - 1) << 16) | (vactive - 1));
837 VML_WRITE32(par, VML_VBLANK_A,
839 VML_WRITE32(par, VML_VSYNC_A,
841 VML_WRITE32(par, VML_DSPCSTRIDE, vinfo->stride);
842 VML_WRITE32(par, VML_DSPCSIZE,
844 VML_WRITE32(par, VML_DSPCPOS, 0x00000000);
845 VML_WRITE32(par, VML_DSPARB, VML_FIFO_DEFAULT);
846 VML_WRITE32(par, VML_BCLRPAT_A, 0x00000000);
847 VML_WRITE32(par, VML_CANVSCLR_A, 0x00000000);
848 VML_WRITE32(par, VML_PIPEASRC,
852 VML_WRITE32(par, VML_PIPEACONF, VML_PIPE_ENABLE);
854 VML_WRITE32(par, VML_DSPCCNTR, dspcntr);
856 VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +
860 VML_WRITE32(par, VML_RCOMPSTAT, VML_MDVO_PAD_ENABLE);
862 while (!(VML_READ32(par, VML_RCOMPSTAT) &
888 struct vml_par *par = vinfo->par;
889 u32 cur = VML_READ32(par, VML_PIPEACONF);
896 VML_WRITE32(par, VML_PIPEACONF, cur & ~VML_PIPE_FORCE_BORDER);
897 (void)VML_READ32(par, VML_PIPEACONF);
903 VML_WRITE32(par, VML_PIPEACONF, cur | VML_PIPE_FORCE_BORDER);
904 (void)VML_READ32(par, VML_PIPEACONF);
940 struct vml_par *par = vinfo->par;
943 VML_WRITE32(par, VML_DSPCADDR, (u32) vinfo->vram_start +
946 (void)VML_READ32(par, VML_DSPCADDR);