Lines Matching defs:par
40 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
42 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
44 (struct tridentfb_par *par, const char*,
174 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
176 fb_writel(v, par->io_virt + r);
179 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
181 return fb_readl(par->io_virt + r);
192 struct tridentfb_par *par = data;
193 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
200 vga_mm_wcrt(par->io_virt, I2C, reg);
205 struct tridentfb_par *par = data;
206 u8 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK_TGUI;
213 vga_mm_wcrt(par->io_virt, I2C, reg);
218 struct tridentfb_par *par = data;
220 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_TGUI);
231 struct tridentfb_par *par = data;
234 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
239 vga_mm_wcrt(par->io_virt, I2C, reg);
244 struct tridentfb_par *par = data;
247 reg = vga_mm_rcrt(par->io_virt, I2C) & DDC_MASK;
252 vga_mm_wcrt(par->io_virt, I2C, reg);
257 struct tridentfb_par *par = data;
259 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SCL_IN);
264 struct tridentfb_par *par = data;
266 return !!(vga_mm_rcrt(par->io_virt, I2C) & DDC_SDA_IN);
271 struct tridentfb_par *par = info->par;
273 strlcpy(par->ddc_adapter.name, info->fix.id,
274 sizeof(par->ddc_adapter.name));
275 par->ddc_adapter.owner = THIS_MODULE;
276 par->ddc_adapter.class = I2C_CLASS_DDC;
277 par->ddc_adapter.algo_data = &par->ddc_algo;
278 par->ddc_adapter.dev.parent = info->device;
279 if (is_oldclock(par->chip_id)) { /* not sure if this check is OK */
280 par->ddc_algo.setsda = tridentfb_ddc_setsda_tgui;
281 par->ddc_algo.setscl = tridentfb_ddc_setscl_tgui;
282 par->ddc_algo.getsda = tridentfb_ddc_getsda_tgui;
285 par->ddc_algo.setsda = tridentfb_ddc_setsda;
286 par->ddc_algo.setscl = tridentfb_ddc_setscl;
287 par->ddc_algo.getsda = tridentfb_ddc_getsda;
288 par->ddc_algo.getscl = tridentfb_ddc_getscl;
290 par->ddc_algo.udelay = 10;
291 par->ddc_algo.timeout = 20;
292 par->ddc_algo.data = par;
294 i2c_set_adapdata(&par->ddc_adapter, par);
296 return i2c_bit_add_bus(&par->ddc_adapter);
305 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
311 writemmr(par, 0x21C0, v2);
312 writemmr(par, 0x21C4, v2);
313 writemmr(par, 0x21B8, v2);
314 writemmr(par, 0x21BC, v2);
315 writemmr(par, 0x21D0, v1);
316 writemmr(par, 0x21D4, v1);
317 writemmr(par, 0x21C8, v1);
318 writemmr(par, 0x21CC, v1);
319 writemmr(par, 0x216C, 0);
322 static void blade_wait_engine(struct tridentfb_par *par)
324 while (readmmr(par, STATUS) & 0xFA800000)
328 static void blade_fill_rect(struct tridentfb_par *par,
331 writemmr(par, COLOR, c);
332 writemmr(par, ROP, rop ? ROP_X : ROP_S);
333 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
335 writemmr(par, DST1, point(x, y));
336 writemmr(par, DST2, point(x + w - 1, y + h - 1));
339 static void blade_image_blit(struct tridentfb_par *par, const char *data,
344 writemmr(par, COLOR, c);
345 writemmr(par, BGCOLOR, b);
346 writemmr(par, CMD, 0xa0000000 | 3 << 19);
348 writemmr(par, DST1, point(x, y));
349 writemmr(par, DST2, point(x + w - 1, y + h - 1));
351 iowrite32_rep(par->io_virt + 0x10000, data, size);
354 static void blade_copy_rect(struct tridentfb_par *par,
366 writemmr(par, ROP, ROP_S);
367 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
369 writemmr(par, SRC1, direction ? s2 : s1);
370 writemmr(par, SRC2, direction ? s1 : s2);
371 writemmr(par, DST1, direction ? d2 : d1);
372 writemmr(par, DST2, direction ? d1 : d2);
379 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
400 t_outb(par, x, 0x2125);
402 par->eng_oper = x | 0x40;
404 writemmr(par, 0x2154, v1);
405 writemmr(par, 0x2150, v1);
406 t_outb(par, 3, 0x2126);
409 static void xp_wait_engine(struct tridentfb_par *par)
414 while (t_inb(par, STATUS) & 0x80) {
422 t_outb(par, 0x00, STATUS);
430 static void xp_fill_rect(struct tridentfb_par *par,
433 writemmr(par, 0x2127, ROP_P);
434 writemmr(par, 0x2158, c);
435 writemmr(par, DRAWFL, 0x4000);
436 writemmr(par, OLDDIM, point(h, w));
437 writemmr(par, OLDDST, point(y, x));
438 t_outb(par, 0x01, OLDCMD);
439 t_outb(par, par->eng_oper, 0x2125);
442 static void xp_copy_rect(struct tridentfb_par *par,
466 writemmr(par, DRAWFL, direction);
467 t_outb(par, ROP_S, 0x2127);
468 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
469 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
470 writemmr(par, OLDDIM, point(h, w));
471 t_outb(par, 0x01, OLDCMD);
477 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
481 writemmr(par, 0x2120, 0xF0000000);
482 writemmr(par, 0x2120, 0x40000000 | tmp);
483 writemmr(par, 0x2120, 0x80000000);
484 writemmr(par, 0x2144, 0x00000000);
485 writemmr(par, 0x2148, 0x00000000);
486 writemmr(par, 0x2150, 0x00000000);
487 writemmr(par, 0x2154, 0x00000000);
488 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
489 writemmr(par, 0x216C, 0x00000000);
490 writemmr(par, 0x2170, 0x00000000);
491 writemmr(par, 0x217C, 0x00000000);
492 writemmr(par, 0x2120, 0x10000000);
493 writemmr(par, 0x2130, (2047 << 16) | 2047);
496 static void image_wait_engine(struct tridentfb_par *par)
498 while (readmmr(par, 0x2164) & 0xF0000000)
502 static void image_fill_rect(struct tridentfb_par *par,
505 writemmr(par, 0x2120, 0x80000000);
506 writemmr(par, 0x2120, 0x90000000 | ROP_S);
508 writemmr(par, 0x2144, c);
510 writemmr(par, DST1, point(x, y));
511 writemmr(par, DST2, point(x + w - 1, y + h - 1));
513 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
516 static void image_copy_rect(struct tridentfb_par *par,
528 writemmr(par, 0x2120, 0x80000000);
529 writemmr(par, 0x2120, 0x90000000 | ROP_S);
531 writemmr(par, SRC1, direction ? s2 : s1);
532 writemmr(par, SRC2, direction ? s1 : s2);
533 writemmr(par, DST1, direction ? d2 : d1);
534 writemmr(par, DST2, direction ? d1 : d2);
535 writemmr(par, 0x2124,
543 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
548 writemmr(par, 0x2148, 0);
549 writemmr(par, 0x214C, point(4095, 2047));
567 fb_writew(x, par->io_virt + 0x2122);
570 static void tgui_fill_rect(struct tridentfb_par *par,
573 t_outb(par, ROP_P, 0x2127);
574 writemmr(par, OLDCLR, c);
575 writemmr(par, DRAWFL, 0x4020);
576 writemmr(par, OLDDIM, point(w - 1, h - 1));
577 writemmr(par, OLDDST, point(x, y));
578 t_outb(par, 1, OLDCMD);
581 static void tgui_copy_rect(struct tridentfb_par *par,
605 writemmr(par, DRAWFL, 0x4 | flags);
606 t_outb(par, ROP_S, 0x2127);
607 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
608 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
609 writemmr(par, OLDDIM, point(w - 1, h - 1));
610 t_outb(par, 1, OLDCMD);
619 struct tridentfb_par *par = info->par;
633 par->wait_engine(par);
634 par->fill_rect(par, fr->dx, fr->dy, fr->width,
641 struct tridentfb_par *par = info->par;
660 par->wait_engine(par);
661 if (par->image_blit)
662 par->image_blit(par, img->data, img->dx, img->dy,
671 struct tridentfb_par *par = info->par;
677 par->wait_engine(par);
678 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
684 struct tridentfb_par *par = info->par;
687 par->wait_engine(par);
695 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
697 return vga_mm_rcrt(par->io_virt, reg);
700 static inline void write3X4(struct tridentfb_par *par, int reg,
703 vga_mm_wcrt(par->io_virt, reg, val);
706 static inline unsigned char read3CE(struct tridentfb_par *par,
709 return vga_mm_rgfx(par->io_virt, reg);
712 static inline void writeAttr(struct tridentfb_par *par, int reg,
715 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
716 vga_mm_wattr(par->io_virt, reg, val);
719 static inline void write3CE(struct tridentfb_par *par, int reg,
722 vga_mm_wgfx(par->io_virt, reg, val);
725 static void enable_mmio(struct tridentfb_par *par)
732 if (!is_oldprotect(par->chip_id))
740 static void disable_mmio(struct tridentfb_par *par)
743 vga_mm_rseq(par->io_virt, 0x0B);
746 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
747 if (!is_oldprotect(par->chip_id))
748 vga_mm_wseq(par->io_virt, Protection, 0x92);
751 t_outb(par, PCIReg, 0x3D4);
752 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
755 static inline void crtc_unlock(struct tridentfb_par *par)
757 write3X4(par, VGA_CRTC_V_SYNC_END,
758 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
762 static int get_nativex(struct tridentfb_par *par)
769 tmp = (read3CE(par, VertStretch) >> 4) & 3;
792 static inline void set_lwidth(struct tridentfb_par *par, int width)
794 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
797 if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
798 write3X4(par, AddColReg,
799 (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
801 write3X4(par, AddColReg,
802 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
806 static void screen_stretch(struct tridentfb_par *par)
808 if (par->chip_id != CYBERBLADEXPAi1)
809 write3CE(par, BiosReg, 0);
811 write3CE(par, BiosReg, 8);
812 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
813 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
817 static inline void screen_center(struct tridentfb_par *par)
819 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
820 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
824 static void set_screen_start(struct tridentfb_par *par, int base)
827 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
828 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
829 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
830 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
831 tmp = read3X4(par, CRTHiOrd) & 0xF8;
832 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
836 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
842 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
862 if (is_oldclock(par->chip_id)) {
870 if (is3Dchip(par->chip_id)) {
871 vga_mm_wseq(par->io_virt, ClockHigh, hi);
872 vga_mm_wseq(par->io_virt, ClockLow, lo);
874 t_outb(par, lo, 0x43C8);
875 t_outb(par, hi, 0x43C9);
881 static void set_number_of_lines(struct tridentfb_par *par, int lines)
883 int tmp = read3CE(par, CyberEnhance) & 0x8F;
892 write3CE(par, CyberEnhance, tmp);
899 static int is_flatpanel(struct tridentfb_par *par)
903 if (crt || !iscyber(par->chip_id))
905 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
909 static unsigned int get_memsize(struct tridentfb_par *par)
918 switch (par->chip_id) {
923 tmp = read3X4(par, SPR) & 0x0F;
955 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
993 struct tridentfb_par *par = info->par;
1004 if (par->chip_id == TGUI9440 && bpp == 32)
1007 if (par->flatpanel && nativex && var->xres > nativex)
1022 if (!is3Dchip(par->chip_id) &&
1075 if (is_xp(par->chip_id))
1078 switch (par->chip_id) {
1111 struct tridentfb_par *par = info->par;
1117 set_screen_start(par, offset);
1122 static inline void shadowmode_on(struct tridentfb_par *par)
1124 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1127 static inline void shadowmode_off(struct tridentfb_par *par)
1129 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1135 struct tridentfb_par *par = info->par;
1168 enable_mmio(par);
1169 crtc_unlock(par);
1170 write3CE(par, CyberControl, 8);
1177 if (par->flatpanel && var->xres < nativex) {
1183 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1185 shadowmode_on(par);
1188 screen_center(par);
1190 screen_stretch(par);
1193 t_outb(par, tmp, VGA_MIS_W);
1194 write3CE(par, CyberControl, 8);
1198 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1199 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1200 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1201 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1202 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1203 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1206 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1207 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1208 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1209 write3X4(par, VGA_CRTC_H_SYNC_END,
1211 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1212 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1224 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1226 tmp = read3X4(par, CRTHiOrd) & 0x07;
1232 write3X4(par, CRTHiOrd, tmp);
1238 write3X4(par, HorizOverflow, tmp);
1243 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1245 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1246 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1247 write3X4(par, VGA_CRTC_MODE, 0xC3);
1249 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1253 write3X4(par, CRTCModuleTest, tmp);
1254 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1257 write3CE(par, MiscIntContReg, tmp);
1260 write3X4(par, GraphEngReg, 0x80);
1277 write3X4(par, PixelBusReg, tmp);
1279 tmp = read3X4(par, DRAMControl);
1280 if (!is_oldprotect(par->chip_id))
1282 if (iscyber(par->chip_id))
1284 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1286 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1287 if (!is_xp(par->chip_id))
1288 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1290 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1291 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1293 vga_mm_wseq(par->io_virt, 0, 3);
1294 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1296 vga_mm_wseq(par->io_virt, 2, 0x0F);
1297 vga_mm_wseq(par->io_virt, 3, 0);
1298 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1304 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1305 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1309 set_vclk(par, vclk);
1310 write3CE(par, MiscExtFunc, tmp | 0x12);
1311 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1312 write3CE(par, 0x6, 0x05); /* graphics mode */
1313 write3CE(par, 0x7, 0x0F); /* planes? */
1316 writeAttr(par, 0x10, 0x41);
1317 writeAttr(par, 0x12, 0x0F); /* planes */
1318 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1322 writeAttr(par, tmp, tmp);
1323 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1324 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1339 t_inb(par, VGA_PEL_IW);
1340 t_inb(par, VGA_PEL_MSK);
1341 t_inb(par, VGA_PEL_MSK);
1342 t_inb(par, VGA_PEL_MSK);
1343 t_inb(par, VGA_PEL_MSK);
1344 t_outb(par, tmp, VGA_PEL_MSK);
1345 t_inb(par, VGA_PEL_IW);
1347 if (par->flatpanel)
1348 set_number_of_lines(par, info->var.yres);
1350 set_lwidth(par, info->fix.line_length / 8);
1353 par->init_accel(par, info->var.xres_virtual, bpp);
1367 struct tridentfb_par *par = info->par;
1373 t_outb(par, 0xFF, VGA_PEL_MSK);
1374 t_outb(par, regno, VGA_PEL_IW);
1376 t_outb(par, red >> 10, VGA_PEL_D);
1377 t_outb(par, green >> 10, VGA_PEL_D);
1378 t_outb(par, blue >> 10, VGA_PEL_D);
1403 struct tridentfb_par *par = info->par;
1406 if (par->flatpanel)
1408 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1409 PMCont = t_inb(par, 0x83C6) & 0xFC;
1410 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1436 write3CE(par, PowerStatus, DPMSCont);
1437 t_outb(par, 4, 0x83C8);
1438 t_outb(par, PMCont, 0x83C6);
1477 default_par = info->par;
1577 disable_mmio(info->par);
1711 disable_mmio(info->par);
1723 struct tridentfb_par *par = info->par;
1726 if (par->ddc_registered)
1727 i2c_del_adapter(&par->ddc_adapter);
1728 iounmap(par->io_virt);