Lines Matching refs:tdfx_inl
243 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
257 while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
270 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
285 tdfx_inl(par, DACADDR);
345 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
405 u32 draminit0 = tdfx_inl(par, DRAMINIT0);
406 u32 draminit1 = tdfx_inl(par, DRAMINIT1);
425 miscinit1 = tdfx_inl(par, MISCINIT1);
684 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
706 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
793 u32 dacmode = tdfx_inl(par, DACMODE);
1055 vidcfg = tdfx_inl(par, VIDPROCCFG);
1174 r = tdfx_inl(par, VIDSERPARPORT);
1180 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1189 r = tdfx_inl(par, VIDSERPARPORT);
1195 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1207 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN));
1215 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN));
1224 r = tdfx_inl(par, VIDSERPARPORT);
1230 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1239 r = tdfx_inl(par, VIDSERPARPORT);
1245 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1253 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN));
1261 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN));