Lines Matching refs:reg

159 static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
161 	return inb(par->iobase + reg - 0x300);
164 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
166 	outb(val, par->iobase + reg - 0x300);
243 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
245 	return readl(par->regbase_virt + reg);
248 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
250 	writel(val, par->regbase_virt + reg);
338 static void do_write_regs(struct fb_info *info, struct banshee_reg *reg)
350 	tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
351 	tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
353 	tdfx_outl(par, PLLCTRL1, reg->mempll);
354 	tdfx_outl(par, PLLCTRL2, reg->gfxpll);
356 	tdfx_outl(par, PLLCTRL0, reg->vidpll);
358 	vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
361 		seq_outb(par, i, reg->seq[i]);
364 		crt_outb(par, i, reg->crt[i]);
367 		gra_outb(par, i, reg->gra[i]);
370 		att_outb(par, i, reg->att[i]);
372 	crt_outb(par, 0x1a, reg->ext[0]);
373 	crt_outb(par, 0x1b, reg->ext[1]);
379 	tdfx_outl(par, VGAINIT0, reg->vgainit0);
380 	tdfx_outl(par, DACMODE, reg->dacmode);
381 	tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
382 	tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
384 	tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
385 	tdfx_outl(par, VIDDESKSTART, reg->startaddr);
386 	tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
387 	tdfx_outl(par, VGAINIT1, reg->vgainit1);
388 	tdfx_outl(par, MISCINIT0, reg->miscinit0);
391 	tdfx_outl(par, SRCBASE, reg->startaddr);
392 	tdfx_outl(par, DSTBASE, reg->startaddr);
553 	struct banshee_reg reg;
558 	memset(&reg, 0, sizeof(reg));
560 	reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE |
568 	reg.vidcfg &= ~VIDCFG_2X;
572 		reg.dacmode |= DACMODE_2X;
573 		reg.vidcfg  |= VIDCFG_2X;
593 		reg.screensize = info->var.xres | (info->var.yres << 13);
594 		reg.vidcfg |= VIDCFG_HALF_MODE;
595 		reg.crt[0x09] = 0x80;
601 		reg.screensize = info->var.xres | (info->var.yres << 12);
602 		reg.vidcfg &= ~VIDCFG_HALF_MODE;
608 	reg.misc[0x00] = 0x0f |
613 	reg.gra[0x05] = 0x40;
614 	reg.gra[0x06] = 0x05;
615 	reg.gra[0x07] = 0x0f;
616 	reg.gra[0x08] = 0xff;
618 	reg.att[0x00] = 0x00;
619 	reg.att[0x01] = 0x01;
620 	reg.att[0x02] = 0x02;
621 	reg.att[0x03] = 0x03;
622 	reg.att[0x04] = 0x04;
623 	reg.att[0x05] = 0x05;
624 	reg.att[0x06] = 0x06;
625 	reg.att[0x07] = 0x07;
626 	reg.att[0x08] = 0x08;
627 	reg.att[0x09] = 0x09;
628 	reg.att[0x0a] = 0x0a;
629 	reg.att[0x0b] = 0x0b;
630 	reg.att[0x0c] = 0x0c;
631 	reg.att[0x0d] = 0x0d;
632 	reg.att[0x0e] = 0x0e;
633 	reg.att[0x0f] = 0x0f;
634 	reg.att[0x10] = 0x41;
635 	reg.att[0x12] = 0x0f;
637 	reg.seq[0x00] = 0x03;
638 	reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
639 	reg.seq[0x02] = 0x0f;
640 	reg.seq[0x03] = 0x00;
641 	reg.seq[0x04] = 0x0e;
643 	reg.crt[0x00] = ht - 4;
644 	reg.crt[0x01] = hd;
645 	reg.crt[0x02] = hbs;
646 	reg.crt[0x03] = 0x80 | (hbe & 0x1f);
647 	reg.crt[0x04] = hs;
648 	reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
649 	reg.crt[0x06] = vt;
650 	reg.crt[0x07] = ((vs & 0x200) >> 2) |
657 	reg.crt[0x09] |= 0x40 | ((vbs & 0x200) >> 4);
658 	reg.crt[0x10] = vs;
659 	reg.crt[0x11] = (ve & 0x0f) | 0x20;
660 	reg.crt[0x12] = vd;
661 	reg.crt[0x13] = wd;
662 	reg.crt[0x15] = vbs;
663 	reg.crt[0x16] = vbe + 1;
664 	reg.crt[0x17] = 0xc3;
665 	reg.crt[0x18] = 0xff;
668 	reg.ext[0x00] = (((ht & 0x100) >> 8) |
674 	reg.ext[0x01] = (((vt & 0x400) >> 10) |
679 	reg.vgainit0 =	VGAINIT0_8BIT_DAC     |
684 	reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
687 		reg.curspataddr = info->fix.smem_len;
689 	reg.cursloc   = 0;
691 	reg.cursc0    = 0;
692 	reg.cursc1    = 0xffffff;
694 	reg.stride    = info->var.xres * cpp;
695 	reg.startaddr = info->var.yoffset * reg.stride
698 	reg.vidpll = do_calc_pll(freq, &fout);
700 	reg.mempll = do_calc_pll(..., &fout);
701 	reg.gfxpll = do_calc_pll(..., &fout);
705 		reg.vidcfg |= VIDCFG_INTERLACE;
706 	reg.miscinit0 = tdfx_inl(par, MISCINIT0);
712 		reg.miscinit0 &= ~(1 << 30);
713 		reg.miscinit0 &= ~(1 << 31);
716 		reg.miscinit0 |= (1 << 30);
717 		reg.miscinit0 |= (1 << 31);
720 		reg.miscinit0 |= (1 << 30);
721 		reg.miscinit0 &= ~(1 << 31);
725 	do_write_regs(info, &reg);
728 	info->fix.line_length = reg.stride;