Lines Matching defs:par
159 static inline u8 vga_inb(struct tdfx_par *par, u32 reg)
161 return inb(par->iobase + reg - 0x300);
164 static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val)
166 outb(val, par->iobase + reg - 0x300);
169 static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val)
171 vga_outb(par, GRA_I, idx);
173 vga_outb(par, GRA_D, val);
177 static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val)
179 vga_outb(par, SEQ_I, idx);
181 vga_outb(par, SEQ_D, val);
185 static inline u8 seq_inb(struct tdfx_par *par, u32 idx)
187 vga_outb(par, SEQ_I, idx);
189 return vga_inb(par, SEQ_D);
192 static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val)
194 vga_outb(par, CRT_I, idx);
196 vga_outb(par, CRT_D, val);
200 static inline u8 crt_inb(struct tdfx_par *par, u32 idx)
202 vga_outb(par, CRT_I, idx);
204 return vga_inb(par, CRT_D);
207 static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
211 tmp = vga_inb(par, IS1_R);
212 vga_outb(par, ATT_IW, idx);
213 vga_outb(par, ATT_IW, val);
216 static inline void vga_disable_video(struct tdfx_par *par)
220 s = seq_inb(par, 0x01) | 0x20;
221 seq_outb(par, 0x00, 0x01);
222 seq_outb(par, 0x01, s);
223 seq_outb(par, 0x00, 0x03);
226 static inline void vga_enable_video(struct tdfx_par *par)
230 s = seq_inb(par, 0x01) & 0xdf;
231 seq_outb(par, 0x00, 0x01);
232 seq_outb(par, 0x01, s);
233 seq_outb(par, 0x00, 0x03);
236 static inline void vga_enable_palette(struct tdfx_par *par)
238 vga_inb(par, IS1_R);
240 vga_outb(par, ATT_IW, 0x20);
243 static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
245 return readl(par->regbase_virt + reg);
248 static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
250 writel(val, par->regbase_virt + reg);
253 static inline void banshee_make_room(struct tdfx_par *par, int size)
257 while ((tdfx_inl(par, STATUS) & 0x1f) < size - 1)
263 struct tdfx_par *par = info->par;
266 banshee_make_room(par, 1);
267 tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
270 if ((tdfx_inl(par, STATUS) & STATUS_BUSY) == 0)
280 static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
282 banshee_make_room(par, 2);
283 tdfx_outl(par, DACADDR, regno);
285 tdfx_inl(par, DACADDR);
286 tdfx_outl(par, DACDATA, c);
340 struct tdfx_par *par = info->par;
345 tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
347 crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
349 banshee_make_room(par, 3);
350 tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
351 tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
353 tdfx_outl(par, PLLCTRL1, reg->mempll);
354 tdfx_outl(par, PLLCTRL2, reg->gfxpll);
356 tdfx_outl(par, PLLCTRL0, reg->vidpll);
358 vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
361 seq_outb(par, i, reg->seq[i]);
364 crt_outb(par, i, reg->crt[i]);
367 gra_outb(par, i, reg->gra[i]);
370 att_outb(par, i, reg->att[i]);
372 crt_outb(par, 0x1a, reg->ext[0]);
373 crt_outb(par, 0x1b, reg->ext[1]);
375 vga_enable_palette(par);
376 vga_enable_video(par);
378 banshee_make_room(par, 9);
379 tdfx_outl(par, VGAINIT0, reg->vgainit0);
380 tdfx_outl(par, DACMODE, reg->dacmode);
381 tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
382 tdfx_outl(par, HWCURPATADDR, reg->curspataddr);
384 tdfx_outl(par, VIDSCREENSIZE, reg->screensize);
385 tdfx_outl(par, VIDDESKSTART, reg->startaddr);
386 tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
387 tdfx_outl(par, VGAINIT1, reg->vgainit1);
388 tdfx_outl(par, MISCINIT0, reg->miscinit0);
390 banshee_make_room(par, 8);
391 tdfx_outl(par, SRCBASE, reg->startaddr);
392 tdfx_outl(par, DSTBASE, reg->startaddr);
393 tdfx_outl(par, COMMANDEXTRA_2D, 0);
394 tdfx_outl(par, CLIP0MIN, 0);
395 tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
396 tdfx_outl(par, CLIP1MIN, 0);
397 tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
398 tdfx_outl(par, SRCXY, 0);
403 static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
405 u32 draminit0 = tdfx_inl(par, DRAMINIT0);
406 u32 draminit1 = tdfx_inl(par, DRAMINIT1);
425 miscinit1 = tdfx_inl(par, MISCINIT1);
429 banshee_make_room(par, 1);
430 tdfx_outl(par, MISCINIT1, miscinit1);
438 struct tdfx_par *par = info->par;
466 (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
500 if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
546 struct tdfx_par *par = info->par;
570 if (freq > par->max_pixclock / 2) {
571 freq = freq > par->max_pixclock ? par->max_pixclock : freq;
684 reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
706 reg.miscinit0 = tdfx_inl(par, MISCINIT0);
727 /* Now change fb_fix_screeninfo according to changes in par */
744 struct tdfx_par *par = info->par;
763 do_setpalentry(par, regno, rgbcol);
776 par->palette[regno] = rgbcol;
791 struct tdfx_par *par = info->par;
793 u32 dacmode = tdfx_inl(par, DACMODE);
814 banshee_make_room(par, 1);
815 tdfx_outl(par, DACMODE, dacmode);
817 vga_disable_video(par);
819 vga_enable_video(par);
829 struct tdfx_par *par = info->par;
835 banshee_make_room(par, 1);
836 tdfx_outl(par, VIDDESKSTART, addr);
848 struct tdfx_par *par = info->par;
872 banshee_make_room(par, 6);
873 tdfx_outl(par, DSTFORMAT, fmt);
875 tdfx_outl(par, COLORFORE, rect->color);
877 tdfx_outl(par, COLORFORE, par->palette[rect->color]);
879 tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
880 tdfx_outl(par, DSTBASE, dstbase);
881 tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
882 tdfx_outl(par, LAUNCH_2D, dx | (dy << 16));
891 struct tdfx_par *par = info->par;
934 banshee_make_room(par, 8);
936 tdfx_outl(par, SRCFORMAT, fmt);
937 tdfx_outl(par, DSTFORMAT, fmt);
938 tdfx_outl(par, COMMAND_2D, blitcmd);
939 tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
940 tdfx_outl(par, DSTXY, dx | (dy << 16));
941 tdfx_outl(par, SRCBASE, srcbase);
942 tdfx_outl(par, DSTBASE, dstbase);
943 tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
948 struct tdfx_par *par = info->par;
962 banshee_make_room(par, 6 + ((size + 3) >> 2));
970 banshee_make_room(par, 9);
973 tdfx_outl(par, COLORFORE, image->fg_color);
974 tdfx_outl(par, COLORBACK, image->bg_color);
978 tdfx_outl(par, COLORFORE,
979 par->palette[image->fg_color]);
980 tdfx_outl(par, COLORBACK,
981 par->palette[image->bg_color]);
999 tdfx_outl(par, DSTBASE, dstbase);
1000 tdfx_outl(par, SRCXY, 0);
1001 tdfx_outl(par, DSTXY, dx | (dy << 16));
1002 tdfx_outl(par, COMMAND_2D,
1004 tdfx_outl(par, SRCFORMAT, srcfmt);
1005 tdfx_outl(par, DSTFORMAT, dstfmt);
1006 tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
1016 banshee_make_room(par, fifo_free);
1018 tdfx_outl(par, LAUNCH_2D, *(u32 *)chardata);
1023 banshee_make_room(par, 3);
1028 tdfx_outl(par, LAUNCH_2D, *chardata);
1031 tdfx_outl(par, LAUNCH_2D, *(u16 *)chardata);
1034 tdfx_outl(par, LAUNCH_2D,
1043 struct tdfx_par *par = info->par;
1055 vidcfg = tdfx_inl(par, VIDPROCCFG);
1057 tdfx_outl(par, VIDPROCCFG, vidcfg | VIDCFG_HWCURSOR_ENABLE);
1059 tdfx_outl(par, VIDPROCCFG, vidcfg & ~VIDCFG_HWCURSOR_ENABLE);
1082 banshee_make_room(par, 2);
1083 tdfx_outl(par, HWCURC0, bg_color);
1084 tdfx_outl(par, HWCURC1, fg_color);
1093 banshee_make_room(par, 1);
1094 tdfx_outl(par, HWCURLOC, (y << 16) + x);
1171 struct tdfx_par *par = chan->par;
1174 r = tdfx_inl(par, VIDSERPARPORT);
1179 tdfx_outl(par, VIDSERPARPORT, r);
1180 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1186 struct tdfx_par *par = chan->par;
1189 r = tdfx_inl(par, VIDSERPARPORT);
1194 tdfx_outl(par, VIDSERPARPORT, r);
1195 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1205 struct tdfx_par *par = chan->par;
1207 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SCL_IN));
1213 struct tdfx_par *par = chan->par;
1215 return (0 != (tdfx_inl(par, VIDSERPARPORT) & I2C_SDA_IN));
1221 struct tdfx_par *par = chan->par;
1224 r = tdfx_inl(par, VIDSERPARPORT);
1229 tdfx_outl(par, VIDSERPARPORT, r);
1230 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1236 struct tdfx_par *par = chan->par;
1239 r = tdfx_inl(par, VIDSERPARPORT);
1244 tdfx_outl(par, VIDSERPARPORT, r);
1245 tdfx_inl(par, VIDSERPARPORT); /* flush posted write */
1251 struct tdfx_par *par = chan->par;
1253 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SCL_IN));
1259 struct tdfx_par *par = chan->par;
1261 return (0 != (tdfx_inl(par, VIDSERPARPORT) & DDC_SDA_IN));
1288 chan->par = NULL;
1316 chan->par = NULL;
1323 struct tdfx_par *par = info->par;
1325 tdfx_outl(par, VIDINFORMAT, 0x8160);
1326 tdfx_outl(par, VIDSERPARPORT, 0xcffc0020);
1328 par->chan[0].par = par;
1329 par->chan[1].par = par;
1331 tdfxfb_setup_ddc_bus(&par->chan[0], "Voodoo3-DDC", info->dev);
1332 tdfxfb_setup_i2c_bus(&par->chan[1], "Voodoo3-I2C", info->dev);
1335 static void tdfxfb_delete_i2c_busses(struct tdfx_par *par)
1337 if (par->chan[0].par)
1338 i2c_del_adapter(&par->chan[0].adapter);
1339 par->chan[0].par = NULL;
1341 if (par->chan[1].par)
1342 i2c_del_adapter(&par->chan[1].adapter);
1343 par->chan[1].par = NULL;
1346 static int tdfxfb_probe_i2c_connector(struct tdfx_par *par,
1352 if (par->chan[0].par)
1353 edid = fb_ddc_read(&par->chan[0].adapter);
1392 default_par = info->par;
1607 struct tdfx_par *par = info->par;
1611 tdfxfb_delete_i2c_busses(par);
1613 arch_phys_wc_del(par->wc_cookie);
1614 iounmap(par->regbase_virt);