Lines Matching refs:status
34 #define check_warn(status, fmt, args...) \
35 ({ if (status < 0) pr_warn(fmt, ##args); })
37 #define check_warn_return(status, fmt, args...) \
38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
40 #define check_warn_goto_error(status, fmt, args...) \
41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
199 int status = ufx_reg_read(dev, index, &data);
200 check_warn_return(status, "ufx_reg_clear_and_set_bits error reading "
206 status = ufx_reg_write(dev, index, data);
207 check_warn_return(status, "ufx_reg_clear_and_set_bits error writing "
225 int status;
228 status = ufx_reg_write(dev, 0x3008, 0x00000001);
229 check_warn_return(status, "ufx_lite_reset error writing 0x3008");
231 status = ufx_reg_read(dev, 0x3008, &value);
232 check_warn_return(status, "ufx_lite_reset error reading 0x3008");
243 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
244 check_warn_return(status, "ufx_blank error reading 0x2004");
246 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
247 check_warn_return(status, "ufx_blank error reading 0x2000");
255 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
256 check_warn_return(status, "ufx_blank error writing 0x2000");
263 status = ufx_reg_read(dev, 0x2004, &dc_sts);
264 check_warn_return(status, "ufx_blank error reading 0x2004");
280 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
281 check_warn_return(status, "ufx_unblank error reading 0x2004");
283 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
284 check_warn_return(status, "ufx_unblank error reading 0x2000");
292 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
293 check_warn_return(status, "ufx_unblank error writing 0x2000");
300 status = ufx_reg_read(dev, 0x2004, &dc_sts);
301 check_warn_return(status, "ufx_unblank error reading 0x2004");
317 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
318 check_warn_return(status, "ufx_disable error reading 0x2004");
320 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
321 check_warn_return(status, "ufx_disable error reading 0x2000");
329 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
330 check_warn_return(status, "ufx_disable error writing 0x2000");
337 status = ufx_reg_read(dev, 0x2004, &dc_sts);
338 check_warn_return(status, "ufx_disable error reading 0x2004");
354 int status = ufx_reg_read(dev, 0x2004, &dc_sts);
355 check_warn_return(status, "ufx_enable error reading 0x2004");
357 status = ufx_reg_read(dev, 0x2000, &dc_ctrl);
358 check_warn_return(status, "ufx_enable error reading 0x2000");
366 status = ufx_reg_write(dev, 0x2000, dc_ctrl);
367 check_warn_return(status, "ufx_enable error writing 0x2000");
374 status = ufx_reg_read(dev, 0x2004, &dc_sts);
375 check_warn_return(status, "ufx_enable error reading 0x2004");
387 int status = ufx_reg_write(dev, 0x700C, 0x8000000F);
388 check_warn_return(status, "error writing 0x700C");
390 status = ufx_reg_write(dev, 0x7014, 0x0010024F);
391 check_warn_return(status, "error writing 0x7014");
393 status = ufx_reg_write(dev, 0x7010, 0x00000000);
394 check_warn_return(status, "error writing 0x7010");
396 status = ufx_reg_clear_bits(dev, 0x700C, 0x0000000A);
397 check_warn_return(status, "error clearing PLL1 bypass in 0x700C");
400 status = ufx_reg_clear_bits(dev, 0x700C, 0x80000000);
401 check_warn_return(status, "error clearing output gate in 0x700C");
408 int status, i = 0;
411 status = ufx_reg_write(dev, 0x0004, 0x001F0F77);
412 check_warn_return(status, "error writing 0x0004");
414 status = ufx_reg_write(dev, 0x0008, 0xFFF00000);
415 check_warn_return(status, "error writing 0x0008");
417 status = ufx_reg_write(dev, 0x000C, 0x0FFF2222);
418 check_warn_return(status, "error writing 0x000C");
420 status = ufx_reg_write(dev, 0x0010, 0x00030814);
421 check_warn_return(status, "error writing 0x0010");
423 status = ufx_reg_write(dev, 0x0014, 0x00500019);
424 check_warn_return(status, "error writing 0x0014");
426 status = ufx_reg_write(dev, 0x0018, 0x020D0F15);
427 check_warn_return(status, "error writing 0x0018");
429 status = ufx_reg_write(dev, 0x001C, 0x02532305);
430 check_warn_return(status, "error writing 0x001C");
432 status = ufx_reg_write(dev, 0x0020, 0x0B030905);
433 check_warn_return(status, "error writing 0x0020");
435 status = ufx_reg_write(dev, 0x0024, 0x00000827);
436 check_warn_return(status, "error writing 0x0024");
438 status = ufx_reg_write(dev, 0x0028, 0x00000000);
439 check_warn_return(status, "error writing 0x0028");
441 status = ufx_reg_write(dev, 0x002C, 0x00000042);
442 check_warn_return(status, "error writing 0x002C");
444 status = ufx_reg_write(dev, 0x0030, 0x09520000);
445 check_warn_return(status, "error writing 0x0030");
447 status = ufx_reg_write(dev, 0x0034, 0x02223314);
448 check_warn_return(status, "error writing 0x0034");
450 status = ufx_reg_write(dev, 0x0038, 0x00430043);
451 check_warn_return(status, "error writing 0x0038");
453 status = ufx_reg_write(dev, 0x003C, 0xF00F000F);
454 check_warn_return(status, "error writing 0x003C");
456 status = ufx_reg_write(dev, 0x0040, 0xF380F00F);
457 check_warn_return(status, "error writing 0x0040");
459 status = ufx_reg_write(dev, 0x0044, 0xF00F0496);
460 check_warn_return(status, "error writing 0x0044");
462 status = ufx_reg_write(dev, 0x0048, 0x03080406);
463 check_warn_return(status, "error writing 0x0048");
465 status = ufx_reg_write(dev, 0x004C, 0x00001000);
466 check_warn_return(status, "error writing 0x004C");
468 status = ufx_reg_write(dev, 0x005C, 0x00000007);
469 check_warn_return(status, "error writing 0x005C");
471 status = ufx_reg_write(dev, 0x0100, 0x54F00012);
472 check_warn_return(status, "error writing 0x0100");
474 status = ufx_reg_write(dev, 0x0104, 0x00004012);
475 check_warn_return(status, "error writing 0x0104");
477 status = ufx_reg_write(dev, 0x0118, 0x40404040);
478 check_warn_return(status, "error writing 0x0118");
480 status = ufx_reg_write(dev, 0x0000, 0x00000001);
481 check_warn_return(status, "error writing 0x0000");
484 status = ufx_reg_read(dev, 0x0000, &tmp);
485 check_warn_return(status, "error reading 0x0000");
618 int status;
630 status = ufx_reg_write(dev, 0x7000, 0x8000000F);
631 check_warn_return(status, "error writing 0x7000");
635 status = ufx_reg_write(dev, 0x7008, value);
636 check_warn_return(status, "error writing 0x7008");
640 status = ufx_reg_write(dev, 0x7004, value);
641 check_warn_return(status, "error writing 0x7004");
643 status = ufx_reg_clear_bits(dev, 0x7000, 0x00000005);
644 check_warn_return(status,
648 status = ufx_reg_clear_bits(dev, 0x7000, 0x0000000A);
649 check_warn_return(status,
653 status = ufx_reg_clear_bits(dev, 0x7000, 0x80000000);
654 check_warn_return(status, "error clearing gate bits in 0x7000");
665 int status = ufx_reg_write(dev, 0x8028, 0);
666 check_warn_return(status, "ufx_set_vid_mode error disabling RGB pad");
668 status = ufx_reg_write(dev, 0x8024, 0);
669 check_warn_return(status, "ufx_set_vid_mode error disabling VDAC");
672 status = ufx_blank(dev, true);
673 check_warn_return(status, "ufx_set_vid_mode error blanking display");
675 status = ufx_disable(dev, true);
676 check_warn_return(status, "ufx_set_vid_mode error disabling display");
678 status = ufx_config_pix_clk(dev, var->pixclock);
679 check_warn_return(status, "ufx_set_vid_mode error configuring pixclock");
681 status = ufx_reg_write(dev, 0x2000, 0x00000104);
682 check_warn_return(status, "ufx_set_vid_mode error writing 0x2000");
693 status = ufx_reg_write(dev, 0x2008, temp);
694 check_warn_return(status, "ufx_set_vid_mode error writing 0x2008");
697 status = ufx_reg_write(dev, 0x200C, temp);
698 check_warn_return(status, "ufx_set_vid_mode error writing 0x200C");
701 status = ufx_reg_write(dev, 0x2010, temp);
702 check_warn_return(status, "ufx_set_vid_mode error writing 0x2010");
713 status = ufx_reg_write(dev, 0x2014, temp);
714 check_warn_return(status, "ufx_set_vid_mode error writing 0x2014");
717 status = ufx_reg_write(dev, 0x2018, temp);
718 check_warn_return(status, "ufx_set_vid_mode error writing 0x2018");
721 status = ufx_reg_write(dev, 0x201C, temp);
722 check_warn_return(status, "ufx_set_vid_mode error writing 0x201C");
724 status = ufx_reg_write(dev, 0x2020, 0x00000000);
725 check_warn_return(status, "ufx_set_vid_mode error writing 0x2020");
727 status = ufx_reg_write(dev, 0x2024, 0x00000000);
728 check_warn_return(status, "ufx_set_vid_mode error writing 0x2024");
733 status = ufx_reg_write(dev, 0x2028, temp);
734 check_warn_return(status, "ufx_set_vid_mode error writing 0x2028");
737 status = ufx_reg_write(dev, 0x2040, 0);
738 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
740 status = ufx_reg_write(dev, 0x2044, 0);
741 check_warn_return(status, "ufx_set_vid_mode error writing 0x2044");
743 status = ufx_reg_write(dev, 0x2048, 0);
744 check_warn_return(status, "ufx_set_vid_mode error writing 0x2048");
754 status = ufx_reg_write(dev, 0x2040, temp);
755 check_warn_return(status, "ufx_set_vid_mode error writing 0x2040");
758 status = ufx_enable(dev, true);
759 check_warn_return(status, "ufx_set_vid_mode error enabling display");
762 status = ufx_unblank(dev, true);
763 check_warn_return(status, "ufx_set_vid_mode error unblanking display");
766 status = ufx_reg_write(dev, 0x8028, 0x00000003);
767 check_warn_return(status, "ufx_set_vid_mode error enabling RGB pad");
770 status = ufx_reg_write(dev, 0x8024, 0x00000007);
771 check_warn_return(status, "ufx_set_vid_mode error enabling VDAC");
854 int len, status, urb_lines, start_line = 0;
885 status = ufx_submit_urb(dev, urb, len);
886 check_warn_return(status, "Error submitting URB");
1340 int status = ufx_reg_write(dev, 0x106C, 0x00);
1341 check_warn_return(status, "failed to disable I2C");
1345 status = ufx_reg_write(dev, 0x1018, 12);
1346 check_warn_return(status, "error writing 0x1018");
1349 status = ufx_reg_write(dev, 0x1014, 6);
1350 check_warn_return(status, "error writing 0x1014");
1352 status = ufx_reg_read(dev, 0x1000, &tmp);
1353 check_warn_return(status, "error reading 0x1000");
1365 status = ufx_reg_write(dev, 0x1000, tmp);
1366 check_warn_return(status, "error writing 0x1000");
1369 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0xC00, 0x000);
1370 check_warn_return(status, "error setting TX mode bits in 0x1004");
1373 status = ufx_reg_write(dev, 0x106C, 0x01);
1374 check_warn_return(status, "failed to enable I2C");
1382 int status = ufx_reg_write(dev, 0x106C, 0x00);
1383 check_warn_return(status, "failed to disable I2C");
1385 status = ufx_reg_write(dev, 0x3010, 0x00000000);
1386 check_warn_return(status, "failed to write 0x3010");
1389 status = ufx_reg_clear_and_set_bits(dev, 0x1004, 0x3FF, (0xA0 >> 1));
1390 check_warn_return(status, "failed to set TAR bits in 0x1004");
1392 status = ufx_reg_write(dev, 0x106C, 0x01);
1393 check_warn_return(status, "failed to enable I2C");
1403 int i, status;
1406 status = ufx_reg_read(dev, 0x1100, &tmp);
1407 check_warn_return(status, "0x1100 read failed");
1425 status = ufx_reg_write(dev, 0x1100, 0x40000000);
1426 check_warn_return(status, "0x1100 write failed");
1434 int i, j, status;
1439 status = ufx_i2c_configure(dev);
1440 if (status < 0) {
1442 return status;
1450 status = ufx_reg_write(dev, 0x1100, temp);
1451 check_warn_return(status, "Failed to write 0x1100");
1454 status = ufx_reg_write(dev, 0x1100, temp);
1455 check_warn_return(status, "Failed to write 0x1100");
1457 status = ufx_i2c_wait_busy(dev);
1458 check_warn_return(status, "Timeout waiting for I2C BUSY to clear");
1462 status = ufx_reg_read(dev, data_reg_addr, edid_u32++);
1463 check_warn_return(status, "Error reading i2c data");
1814 if (urb->status) {
1815 if (!(urb->status == -ENOENT ||
1816 urb->status == -ECONNRESET ||
1817 urb->status == -ESHUTDOWN)) {
1818 pr_err("%s - nonzero write bulk status received: %d\n",
1819 __func__, urb->status);