Lines Matching refs:par
80 static void vgaHWSeqReset(struct savagefb_par *par, int start)
83 VGAwSEQ(0x00, 0x01, par); /* Synchronous Reset */
85 VGAwSEQ(0x00, 0x03, par); /* End Reset */
88 static void vgaHWProtect(struct savagefb_par *par, int on)
96 tmp = VGArSEQ(0x01, par);
98 vgaHWSeqReset(par, 1); /* start synchronous reset */
99 VGAwSEQ(0x01, tmp | 0x20, par);/* disable the display */
101 VGAenablePalette(par);
107 tmp = VGArSEQ(0x01, par);
109 VGAwSEQ(0x01, tmp & ~0x20, par);/* reenable display */
110 vgaHWSeqReset(par, 0); /* clear synchronous reset */
112 VGAdisablePalette(par);
116 static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg)
120 VGAwMISC(reg->MiscOutReg, par);
123 VGAwSEQ(i, reg->Sequencer[i], par);
127 VGAwCR(17, reg->CRTC[17] & ~0x80, par);
130 VGAwCR(i, reg->CRTC[i], par);
133 VGAwGR(i, reg->Graphics[i], par);
135 VGAenablePalette(par);
138 VGAwATTR(i, reg->Attribute[i], par);
140 VGAdisablePalette(par);
144 struct savagefb_par *par,
257 savage3D_waitfifo(struct savagefb_par *par, int space)
261 while ((savage_in32(0x48C00, par) & 0x0000ffff) > slots);
265 savage4_waitfifo(struct savagefb_par *par, int space)
269 while ((savage_in32(0x48C60, par) & 0x001fffff) > slots);
273 savage2000_waitfifo(struct savagefb_par *par, int space)
277 while ((savage_in32(0x48C60, par) & 0x0000ffff) > slots);
282 savage3D_waitidle(struct savagefb_par *par)
284 while ((savage_in32(0x48C00, par) & 0x0008ffff) != 0x80000);
288 savage4_waitidle(struct savagefb_par *par)
290 while ((savage_in32(0x48C60, par) & 0x00a00000) != 0x00a00000);
294 savage2000_waitidle(struct savagefb_par *par)
296 while ((savage_in32(0x48C60, par) & 0x009fffff));
301 SavageSetup2DEngine(struct savagefb_par *par)
306 BCI_BD_SET_BPP(GlobalBitmapDescriptor, par->depth);
307 BCI_BD_SET_STRIDE(GlobalBitmapDescriptor, par->vwidth);
309 switch(par->chip) {
313 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
316 (par->cob_offset >> 11) | (par->cob_index << 29),
317 par);
319 savage_out32(0x48C10, 0x78207220, par);
320 savage_out32(0x48C0C, 0, par);
322 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
330 savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
332 savage_out32(0x48C10, 0x00700040, par);
333 savage_out32(0x48C0C, 0, par);
335 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x08, par);
339 savage_out32(0x48C18, 0, par);
342 (par->cob_offset >> 7) | (par->cob_index),
343 par);
345 savage_out32(0x48A30, 0, par);
347 savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x00280000,
348 par);
354 vga_out8(0x3d4, 0x31, par);
355 vga_out8(0x3d5, 0x0c, par);
358 vga_out8(0x3d4, 0x50, par);
359 vga_out8(0x3d5, vga_in8(0x3d5, par) | 0xC1, par);
362 vga_out8(0x3d4, 0x40, par);
363 vga_out8(0x3d5, 0x01, par);
365 savage_out32(MONO_PAT_0, ~0, par);
366 savage_out32(MONO_PAT_1, ~0, par);
369 savage_out32(0x8128, ~0, par); /* enable all write planes */
370 savage_out32(0x812C, ~0, par); /* enable all read planes */
371 savage_out16(0x8134, 0x27, par);
372 savage_out16(0x8136, 0x07, par);
375 par->bci_ptr = 0;
376 par->SavageWaitFifo(par, 4);
388 par->bci_ptr = 0;
389 par->SavageWaitFifo(par, 4);
399 struct savagefb_par *par = info->par;
403 par->bci_ptr = 0;
404 par->SavageWaitFifo(par,3);
410 static void SavageSetup2DEngine(struct savagefb_par *par) {}
507 static void SavagePrintRegs(struct savagefb_par *par)
519 vga_out8(0x3c4, i, par);
520 printk(KERN_DEBUG " %02x", vga_in8(0x3c5, par));
529 vga_out8(vgaCRIndex, i, par);
530 printk(KERN_DEBUG " %02x", vga_in8(vgaCRReg, par));
539 static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)
543 vga_out16(0x3d4, 0x4838, par);
544 vga_out16(0x3d4, 0xa039, par);
545 vga_out16(0x3c4, 0x0608, par);
547 vga_out8(0x3d4, 0x66, par);
548 cr66 = vga_in8(0x3d5, par);
549 vga_out8(0x3d5, cr66 | 0x80, par);
550 vga_out8(0x3d4, 0x3a, par);
551 cr3a = vga_in8(0x3d5, par);
552 vga_out8(0x3d5, cr3a | 0x80, par);
553 vga_out8(0x3d4, 0x53, par);
554 cr53 = vga_in8(0x3d5, par);
555 vga_out8(0x3d5, cr53 & 0x7f, par);
557 vga_out8(0x3d4, 0x66, par);
558 vga_out8(0x3d5, cr66, par);
559 vga_out8(0x3d4, 0x3a, par);
560 vga_out8(0x3d5, cr3a, par);
562 vga_out8(0x3d4, 0x66, par);
563 vga_out8(0x3d5, cr66, par);
564 vga_out8(0x3d4, 0x3a, par);
565 vga_out8(0x3d5, cr3a, par);
568 vga_out8(0x3c4, 0x08, par);
569 reg->SR08 = vga_in8(0x3c5, par);
570 vga_out8(0x3c5, 0x06, par);
573 vga_out8(0x3d4, 0x31, par);
574 reg->CR31 = vga_in8(0x3d5, par);
575 vga_out8(0x3d4, 0x32, par);
576 reg->CR32 = vga_in8(0x3d5, par);
577 vga_out8(0x3d4, 0x34, par);
578 reg->CR34 = vga_in8(0x3d5, par);
579 vga_out8(0x3d4, 0x36, par);
580 reg->CR36 = vga_in8(0x3d5, par);
581 vga_out8(0x3d4, 0x3a, par);
582 reg->CR3A = vga_in8(0x3d5, par);
583 vga_out8(0x3d4, 0x40, par);
584 reg->CR40 = vga_in8(0x3d5, par);
585 vga_out8(0x3d4, 0x42, par);
586 reg->CR42 = vga_in8(0x3d5, par);
587 vga_out8(0x3d4, 0x45, par);
588 reg->CR45 = vga_in8(0x3d5, par);
589 vga_out8(0x3d4, 0x50, par);
590 reg->CR50 = vga_in8(0x3d5, par);
591 vga_out8(0x3d4, 0x51, par);
592 reg->CR51 = vga_in8(0x3d5, par);
593 vga_out8(0x3d4, 0x53, par);
594 reg->CR53 = vga_in8(0x3d5, par);
595 vga_out8(0x3d4, 0x58, par);
596 reg->CR58 = vga_in8(0x3d5, par);
597 vga_out8(0x3d4, 0x60, par);
598 reg->CR60 = vga_in8(0x3d5, par);
599 vga_out8(0x3d4, 0x66, par);
600 reg->CR66 = vga_in8(0x3d5, par);
601 vga_out8(0x3d4, 0x67, par);
602 reg->CR67 = vga_in8(0x3d5, par);
603 vga_out8(0x3d4, 0x68, par);
604 reg->CR68 = vga_in8(0x3d5, par);
605 vga_out8(0x3d4, 0x69, par);
606 reg->CR69 = vga_in8(0x3d5, par);
607 vga_out8(0x3d4, 0x6f, par);
608 reg->CR6F = vga_in8(0x3d5, par);
610 vga_out8(0x3d4, 0x33, par);
611 reg->CR33 = vga_in8(0x3d5, par);
612 vga_out8(0x3d4, 0x86, par);
613 reg->CR86 = vga_in8(0x3d5, par);
614 vga_out8(0x3d4, 0x88, par);
615 reg->CR88 = vga_in8(0x3d5, par);
616 vga_out8(0x3d4, 0x90, par);
617 reg->CR90 = vga_in8(0x3d5, par);
618 vga_out8(0x3d4, 0x91, par);
619 reg->CR91 = vga_in8(0x3d5, par);
620 vga_out8(0x3d4, 0xb0, par);
621 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
624 vga_out8(0x3d4, 0x3b, par);
625 reg->CR3B = vga_in8(0x3d5, par);
626 vga_out8(0x3d4, 0x3c, par);
627 reg->CR3C = vga_in8(0x3d5, par);
628 vga_out8(0x3d4, 0x43, par);
629 reg->CR43 = vga_in8(0x3d5, par);
630 vga_out8(0x3d4, 0x5d, par);
631 reg->CR5D = vga_in8(0x3d5, par);
632 vga_out8(0x3d4, 0x5e, par);
633 reg->CR5E = vga_in8(0x3d5, par);
634 vga_out8(0x3d4, 0x65, par);
635 reg->CR65 = vga_in8(0x3d5, par);
638 vga_out8(0x3c4, 0x0e, par);
639 reg->SR0E = vga_in8(0x3c5, par);
640 vga_out8(0x3c4, 0x0f, par);
641 reg->SR0F = vga_in8(0x3c5, par);
642 vga_out8(0x3c4, 0x10, par);
643 reg->SR10 = vga_in8(0x3c5, par);
644 vga_out8(0x3c4, 0x11, par);
645 reg->SR11 = vga_in8(0x3c5, par);
646 vga_out8(0x3c4, 0x12, par);
647 reg->SR12 = vga_in8(0x3c5, par);
648 vga_out8(0x3c4, 0x13, par);
649 reg->SR13 = vga_in8(0x3c5, par);
650 vga_out8(0x3c4, 0x29, par);
651 reg->SR29 = vga_in8(0x3c5, par);
653 vga_out8(0x3c4, 0x15, par);
654 reg->SR15 = vga_in8(0x3c5, par);
655 vga_out8(0x3c4, 0x30, par);
656 reg->SR30 = vga_in8(0x3c5, par);
657 vga_out8(0x3c4, 0x18, par);
658 reg->SR18 = vga_in8(0x3c5, par);
661 if (par->chip == S3_SAVAGE_MX) {
665 vga_out8(0x3c4, 0x54+i, par);
666 reg->SR54[i] = vga_in8(0x3c5, par);
670 vga_out8(0x3d4, 0x66, par);
671 cr66 = vga_in8(0x3d5, par);
672 vga_out8(0x3d5, cr66 | 0x80, par);
673 vga_out8(0x3d4, 0x3a, par);
674 cr3a = vga_in8(0x3d5, par);
675 vga_out8(0x3d5, cr3a | 0x80, par);
678 if (par->chip != S3_SAVAGE_MX) {
679 reg->MMPR0 = savage_in32(FIFO_CONTROL_REG, par);
680 reg->MMPR1 = savage_in32(MIU_CONTROL_REG, par);
681 reg->MMPR2 = savage_in32(STREAMS_TIMEOUT_REG, par);
682 reg->MMPR3 = savage_in32(MISC_TIMEOUT_REG, par);
685 vga_out8(0x3d4, 0x3a, par);
686 vga_out8(0x3d5, cr3a, par);
687 vga_out8(0x3d4, 0x66, par);
688 vga_out8(0x3d5, cr66, par);
691 static void savage_set_default_par(struct savagefb_par *par,
696 vga_out16(0x3d4, 0x4838, par);
697 vga_out16(0x3d4, 0xa039, par);
698 vga_out16(0x3c4, 0x0608, par);
700 vga_out8(0x3d4, 0x66, par);
701 cr66 = vga_in8(0x3d5, par);
702 vga_out8(0x3d5, cr66 | 0x80, par);
703 vga_out8(0x3d4, 0x3a, par);
704 cr3a = vga_in8(0x3d5, par);
705 vga_out8(0x3d5, cr3a | 0x80, par);
706 vga_out8(0x3d4, 0x53, par);
707 cr53 = vga_in8(0x3d5, par);
708 vga_out8(0x3d5, cr53 & 0x7f, par);
710 vga_out8(0x3d4, 0x66, par);
711 vga_out8(0x3d5, cr66, par);
712 vga_out8(0x3d4, 0x3a, par);
713 vga_out8(0x3d5, cr3a, par);
715 vga_out8(0x3d4, 0x66, par);
716 vga_out8(0x3d5, cr66, par);
717 vga_out8(0x3d4, 0x3a, par);
718 vga_out8(0x3d5, cr3a, par);
721 vga_out8(0x3c4, 0x08, par);
722 vga_out8(0x3c5, reg->SR08, par);
723 vga_out8(0x3c5, 0x06, par);
726 vga_out8(0x3d4, 0x31, par);
727 vga_out8(0x3d5, reg->CR31, par);
728 vga_out8(0x3d4, 0x32, par);
729 vga_out8(0x3d5, reg->CR32, par);
730 vga_out8(0x3d4, 0x34, par);
731 vga_out8(0x3d5, reg->CR34, par);
732 vga_out8(0x3d4, 0x36, par);
733 vga_out8(0x3d5,reg->CR36, par);
734 vga_out8(0x3d4, 0x3a, par);
735 vga_out8(0x3d5, reg->CR3A, par);
736 vga_out8(0x3d4, 0x40, par);
737 vga_out8(0x3d5, reg->CR40, par);
738 vga_out8(0x3d4, 0x42, par);
739 vga_out8(0x3d5, reg->CR42, par);
740 vga_out8(0x3d4, 0x45, par);
741 vga_out8(0x3d5, reg->CR45, par);
742 vga_out8(0x3d4, 0x50, par);
743 vga_out8(0x3d5, reg->CR50, par);
744 vga_out8(0x3d4, 0x51, par);
745 vga_out8(0x3d5, reg->CR51, par);
746 vga_out8(0x3d4, 0x53, par);
747 vga_out8(0x3d5, reg->CR53, par);
748 vga_out8(0x3d4, 0x58, par);
749 vga_out8(0x3d5, reg->CR58, par);
750 vga_out8(0x3d4, 0x60, par);
751 vga_out8(0x3d5, reg->CR60, par);
752 vga_out8(0x3d4, 0x66, par);
753 vga_out8(0x3d5, reg->CR66, par);
754 vga_out8(0x3d4, 0x67, par);
755 vga_out8(0x3d5, reg->CR67, par);
756 vga_out8(0x3d4, 0x68, par);
757 vga_out8(0x3d5, reg->CR68, par);
758 vga_out8(0x3d4, 0x69, par);
759 vga_out8(0x3d5, reg->CR69, par);
760 vga_out8(0x3d4, 0x6f, par);
761 vga_out8(0x3d5, reg->CR6F, par);
763 vga_out8(0x3d4, 0x33, par);
764 vga_out8(0x3d5, reg->CR33, par);
765 vga_out8(0x3d4, 0x86, par);
766 vga_out8(0x3d5, reg->CR86, par);
767 vga_out8(0x3d4, 0x88, par);
768 vga_out8(0x3d5, reg->CR88, par);
769 vga_out8(0x3d4, 0x90, par);
770 vga_out8(0x3d5, reg->CR90, par);
771 vga_out8(0x3d4, 0x91, par);
772 vga_out8(0x3d5, reg->CR91, par);
773 vga_out8(0x3d4, 0xb0, par);
774 vga_out8(0x3d5, reg->CRB0, par);
777 vga_out8(0x3d4, 0x3b, par);
778 vga_out8(0x3d5, reg->CR3B, par);
779 vga_out8(0x3d4, 0x3c, par);
780 vga_out8(0x3d5, reg->CR3C, par);
781 vga_out8(0x3d4, 0x43, par);
782 vga_out8(0x3d5, reg->CR43, par);
783 vga_out8(0x3d4, 0x5d, par);
784 vga_out8(0x3d5, reg->CR5D, par);
785 vga_out8(0x3d4, 0x5e, par);
786 vga_out8(0x3d5, reg->CR5E, par);
787 vga_out8(0x3d4, 0x65, par);
788 vga_out8(0x3d5, reg->CR65, par);
791 vga_out8(0x3c4, 0x0e, par);
792 vga_out8(0x3c5, reg->SR0E, par);
793 vga_out8(0x3c4, 0x0f, par);
794 vga_out8(0x3c5, reg->SR0F, par);
795 vga_out8(0x3c4, 0x10, par);
796 vga_out8(0x3c5, reg->SR10, par);
797 vga_out8(0x3c4, 0x11, par);
798 vga_out8(0x3c5, reg->SR11, par);
799 vga_out8(0x3c4, 0x12, par);
800 vga_out8(0x3c5, reg->SR12, par);
801 vga_out8(0x3c4, 0x13, par);
802 vga_out8(0x3c5, reg->SR13, par);
803 vga_out8(0x3c4, 0x29, par);
804 vga_out8(0x3c5, reg->SR29, par);
806 vga_out8(0x3c4, 0x15, par);
807 vga_out8(0x3c5, reg->SR15, par);
808 vga_out8(0x3c4, 0x30, par);
809 vga_out8(0x3c5, reg->SR30, par);
810 vga_out8(0x3c4, 0x18, par);
811 vga_out8(0x3c5, reg->SR18, par);
814 if (par->chip == S3_SAVAGE_MX) {
818 vga_out8(0x3c4, 0x54+i, par);
819 vga_out8(0x3c5, reg->SR54[i], par);
823 vga_out8(0x3d4, 0x66, par);
824 cr66 = vga_in8(0x3d5, par);
825 vga_out8(0x3d5, cr66 | 0x80, par);
826 vga_out8(0x3d4, 0x3a, par);
827 cr3a = vga_in8(0x3d5, par);
828 vga_out8(0x3d5, cr3a | 0x80, par);
831 if (par->chip != S3_SAVAGE_MX) {
832 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
833 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
834 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
835 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
838 vga_out8(0x3d4, 0x3a, par);
839 vga_out8(0x3d5, cr3a, par);
840 vga_out8(0x3d4, 0x66, par);
841 vga_out8(0x3d5, cr66, par);
866 struct savagefb_par *par = info->par;
927 if (par->SavagePanelWidth &&
928 (var->xres > par->SavagePanelWidth ||
929 var->yres > par->SavagePanelHeight)) {
932 par->SavagePanelWidth,
933 par->SavagePanelHeight);
969 struct savagefb_par *par,
998 par->depth = var->bits_per_pixel;
999 par->vwidth = var->xres_virtual;
1001 if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) {
1012 vgaHWInit(var, par, &timings, reg);
1021 if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000))
1027 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1028 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1034 if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1035 ((par->chip == S3_SAVAGE2000) && (dclk >= 230000)))
1053 vga_out8(0x3d4, 0x3a, par);
1054 tmp = vga_in8(0x3d5, par);
1064 vga_out8(0x3d4, 0x58, par);
1065 reg->CR58 = vga_in8(0x3d5, par) & 0x80;
1072 vga_out8(0x3d4, 0x40, par);
1073 reg->CR40 = vga_in8(0x3d5, par) & ~0x01;
1083 if (par->MCLK <= 0) {
1087 common_calc_clock(par->MCLK, 1, 1, 31, 0, 3, 135000, 270000,
1168 if (par->chip == S3_SAVAGE2000)
1177 vga_out8(0x3d4, 0x36, par);
1178 reg->CR36 = vga_in8(0x3d5, par);
1179 vga_out8(0x3d4, 0x68, par);
1180 reg->CR68 = vga_in8(0x3d5, par);
1182 vga_out8(0x3d4, 0x6f, par);
1183 reg->CR6F = vga_in8(0x3d5, par);
1184 vga_out8(0x3d4, 0x86, par);
1185 reg->CR86 = vga_in8(0x3d5, par);
1186 vga_out8(0x3d4, 0x88, par);
1187 reg->CR88 = vga_in8(0x3d5, par) | 0x08;
1188 vga_out8(0x3d4, 0xb0, par);
1189 reg->CRB0 = vga_in8(0x3d5, par) | 0x80;
1206 struct savagefb_par *par = info->par;
1211 par->palette[regno].red = red;
1212 par->palette[regno].green = green;
1213 par->palette[regno].blue = blue;
1214 par->palette[regno].transp = transp;
1218 vga_out8(0x3c8, regno, par);
1220 vga_out8(0x3c9, red >> 10, par);
1221 vga_out8(0x3c9, green >> 10, par);
1222 vga_out8(0x3c9, blue >> 10, par);
1256 static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg)
1262 par->SavageWaitIdle(par);
1264 vga_out8(0x3c2, 0x23, par);
1266 vga_out16(0x3d4, 0x4838, par);
1267 vga_out16(0x3d4, 0xa539, par);
1268 vga_out16(0x3c4, 0x0608, par);
1270 vgaHWProtect(par, 1);
1279 VerticalRetraceWait(par);
1280 vga_out8(0x3d4, 0x67, par);
1281 cr67 = vga_in8(0x3d5, par);
1282 vga_out8(0x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */
1284 vga_out8(0x3d4, 0x23, par);
1285 vga_out8(0x3d5, 0x00, par);
1286 vga_out8(0x3d4, 0x26, par);
1287 vga_out8(0x3d5, 0x00, par);
1290 vga_out8(0x3d4, 0x66, par);
1291 vga_out8(0x3d5, reg->CR66, par);
1292 vga_out8(0x3d4, 0x3a, par);
1293 vga_out8(0x3d5, reg->CR3A, par);
1294 vga_out8(0x3d4, 0x31, par);
1295 vga_out8(0x3d5, reg->CR31, par);
1296 vga_out8(0x3d4, 0x32, par);
1297 vga_out8(0x3d5, reg->CR32, par);
1298 vga_out8(0x3d4, 0x58, par);
1299 vga_out8(0x3d5, reg->CR58, par);
1300 vga_out8(0x3d4, 0x53, par);
1301 vga_out8(0x3d5, reg->CR53 & 0x7f, par);
1303 vga_out16(0x3c4, 0x0608, par);
1307 vga_out8(0x3c4, 0x0e, par);
1308 vga_out8(0x3c5, reg->SR0E, par);
1309 vga_out8(0x3c4, 0x0f, par);
1310 vga_out8(0x3c5, reg->SR0F, par);
1311 vga_out8(0x3c4, 0x29, par);
1312 vga_out8(0x3c5, reg->SR29, par);
1313 vga_out8(0x3c4, 0x15, par);
1314 vga_out8(0x3c5, reg->SR15, par);
1317 if (par->chip == S3_SAVAGE_MX) {
1321 vga_out8(0x3c4, 0x54+i, par);
1322 vga_out8(0x3c5, reg->SR54[i], par);
1326 vgaHWRestore (par, reg);
1329 vga_out8(0x3d4, 0x53, par);
1330 vga_out8(0x3d5, reg->CR53, par);
1331 vga_out8(0x3d4, 0x5d, par);
1332 vga_out8(0x3d5, reg->CR5D, par);
1333 vga_out8(0x3d4, 0x5e, par);
1334 vga_out8(0x3d5, reg->CR5E, par);
1335 vga_out8(0x3d4, 0x3b, par);
1336 vga_out8(0x3d5, reg->CR3B, par);
1337 vga_out8(0x3d4, 0x3c, par);
1338 vga_out8(0x3d5, reg->CR3C, par);
1339 vga_out8(0x3d4, 0x43, par);
1340 vga_out8(0x3d5, reg->CR43, par);
1341 vga_out8(0x3d4, 0x65, par);
1342 vga_out8(0x3d5, reg->CR65, par);
1345 vga_out8(0x3d4, 0x67, par);
1347 cr67 = vga_in8(0x3d5, par) & 0xf;
1348 vga_out8(0x3d5, 0x50 | cr67, par);
1350 vga_out8(0x3d4, 0x67, par);
1352 vga_out8(0x3d5, reg->CR67 & ~0x0c, par);
1355 vga_out8(0x3d4, 0x34, par);
1356 vga_out8(0x3d5, reg->CR34, par);
1357 vga_out8(0x3d4, 0x40, par);
1358 vga_out8(0x3d5, reg->CR40, par);
1359 vga_out8(0x3d4, 0x42, par);
1360 vga_out8(0x3d5, reg->CR42, par);
1361 vga_out8(0x3d4, 0x45, par);
1362 vga_out8(0x3d5, reg->CR45, par);
1363 vga_out8(0x3d4, 0x50, par);
1364 vga_out8(0x3d5, reg->CR50, par);
1365 vga_out8(0x3d4, 0x51, par);
1366 vga_out8(0x3d5, reg->CR51, par);
1369 vga_out8(0x3d4, 0x36, par);
1370 vga_out8(0x3d5, reg->CR36, par);
1371 vga_out8(0x3d4, 0x60, par);
1372 vga_out8(0x3d5, reg->CR60, par);
1373 vga_out8(0x3d4, 0x68, par);
1374 vga_out8(0x3d5, reg->CR68, par);
1375 vga_out8(0x3d4, 0x69, par);
1376 vga_out8(0x3d5, reg->CR69, par);
1377 vga_out8(0x3d4, 0x6f, par);
1378 vga_out8(0x3d5, reg->CR6F, par);
1380 vga_out8(0x3d4, 0x33, par);
1381 vga_out8(0x3d5, reg->CR33, par);
1382 vga_out8(0x3d4, 0x86, par);
1383 vga_out8(0x3d5, reg->CR86, par);
1384 vga_out8(0x3d4, 0x88, par);
1385 vga_out8(0x3d5, reg->CR88, par);
1386 vga_out8(0x3d4, 0x90, par);
1387 vga_out8(0x3d5, reg->CR90, par);
1388 vga_out8(0x3d4, 0x91, par);
1389 vga_out8(0x3d5, reg->CR91, par);
1391 if (par->chip == S3_SAVAGE4) {
1392 vga_out8(0x3d4, 0xb0, par);
1393 vga_out8(0x3d5, reg->CRB0, par);
1396 vga_out8(0x3d4, 0x32, par);
1397 vga_out8(0x3d5, reg->CR32, par);
1400 vga_out8(0x3c4, 0x08, par);
1401 vga_out8(0x3c5, 0x06, par);
1407 vga_out8(0x3c4, 0x10, par);
1408 vga_out8(0x3c5, reg->SR10, par);
1409 vga_out8(0x3c4, 0x11, par);
1410 vga_out8(0x3c5, reg->SR11, par);
1414 vga_out8(0x3c4, 0x0e, par);
1415 vga_out8(0x3c5, reg->SR0E, par);
1416 vga_out8(0x3c4, 0x0f, par);
1417 vga_out8(0x3c5, reg->SR0F, par);
1418 vga_out8(0x3c4, 0x12, par);
1419 vga_out8(0x3c5, reg->SR12, par);
1420 vga_out8(0x3c4, 0x13, par);
1421 vga_out8(0x3c5, reg->SR13, par);
1422 vga_out8(0x3c4, 0x29, par);
1423 vga_out8(0x3c5, reg->SR29, par);
1424 vga_out8(0x3c4, 0x18, par);
1425 vga_out8(0x3c5, reg->SR18, par);
1428 vga_out8(0x3c4, 0x15, par);
1429 tmp = vga_in8(0x3c5, par) & ~0x21;
1431 vga_out8(0x3c5, tmp | 0x03, par);
1432 vga_out8(0x3c5, tmp | 0x23, par);
1433 vga_out8(0x3c5, tmp | 0x03, par);
1434 vga_out8(0x3c5, reg->SR15, par);
1437 vga_out8(0x3c4, 0x30, par);
1438 vga_out8(0x3c5, reg->SR30, par);
1439 vga_out8(0x3c4, 0x08, par);
1440 vga_out8(0x3c5, reg->SR08, par);
1443 VerticalRetraceWait(par);
1444 vga_out8(0x3d4, 0x67, par);
1445 vga_out8(0x3d5, reg->CR67, par);
1447 vga_out8(0x3d4, 0x66, par);
1448 cr66 = vga_in8(0x3d5, par);
1449 vga_out8(0x3d5, cr66 | 0x80, par);
1450 vga_out8(0x3d4, 0x3a, par);
1451 cr3a = vga_in8(0x3d5, par);
1452 vga_out8(0x3d5, cr3a | 0x80, par);
1454 if (par->chip != S3_SAVAGE_MX) {
1455 VerticalRetraceWait(par);
1456 savage_out32(FIFO_CONTROL_REG, reg->MMPR0, par);
1457 par->SavageWaitIdle(par);
1458 savage_out32(MIU_CONTROL_REG, reg->MMPR1, par);
1459 par->SavageWaitIdle(par);
1460 savage_out32(STREAMS_TIMEOUT_REG, reg->MMPR2, par);
1461 par->SavageWaitIdle(par);
1462 savage_out32(MISC_TIMEOUT_REG, reg->MMPR3, par);
1465 vga_out8(0x3d4, 0x66, par);
1466 vga_out8(0x3d5, cr66, par);
1467 vga_out8(0x3d4, 0x3a, par);
1468 vga_out8(0x3d5, cr3a, par);
1470 SavageSetup2DEngine(par);
1471 vgaHWProtect(par, 0);
1474 static void savagefb_update_start(struct savagefb_par *par, int base)
1477 vga_out16(0x3d4, (base & 0x00ff00) | 0x0c, par);
1478 vga_out16(0x3d4, ((base & 0x00ff) << 8) | 0x0d, par);
1479 vga_out8(0x3d4, 0x69, par);
1480 vga_out8(0x3d5, (base & 0x7f0000) >> 16, par);
1501 struct savagefb_par *par = info->par;
1506 err = savagefb_decode_var(var, par, &par->state);
1510 if (par->dacSpeedBpp <= 0) {
1512 par->dacSpeedBpp = par->clock[3];
1514 par->dacSpeedBpp = par->clock[2];
1516 par->dacSpeedBpp = par->clock[1];
1518 par->dacSpeedBpp = par->clock[0];
1522 par->maxClock = par->dacSpeedBpp;
1523 par->minClock = 10000;
1525 savagefb_set_par_int(par, &par->state);
1530 SavagePrintRegs(par);
1540 struct savagefb_par *par = info->par;
1546 savagefb_update_start(par, base);
1552 struct savagefb_par *par = info->par;
1555 if (par->display_type == DISP_CRT) {
1556 vga_out8(0x3c4, 0x08, par);
1557 sr8 = vga_in8(0x3c5, par);
1559 vga_out8(0x3c5, sr8, par);
1560 vga_out8(0x3c4, 0x0d, par);
1561 srd = vga_in8(0x3c5, par);
1579 vga_out8(0x3c4, 0x0d, par);
1580 vga_out8(0x3c5, srd, par);
1583 if (par->display_type == DISP_LCD ||
1584 par->display_type == DISP_DFP) {
1588 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1589 vga_out8(0x3c5, vga_in8(0x3c5, par) | 0x10, par);
1594 vga_out8(0x3c4, 0x31, par); /* SR31 bit 4 - FP enable */
1595 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x10, par);
1605 struct savagefb_par *par = info->par;
1607 mutex_lock(&par->open_lock);
1609 if (!par->open_count) {
1610 memset(&par->vgastate, 0, sizeof(par->vgastate));
1611 par->vgastate.flags = VGA_SAVE_CMAP | VGA_SAVE_FONTS |
1613 par->vgastate.vgabase = par->mmio.vbase + 0x8000;
1614 save_vga(&par->vgastate);
1615 savage_get_default_par(par, &par->initial);
1618 par->open_count++;
1619 mutex_unlock(&par->open_lock);
1625 struct savagefb_par *par = info->par;
1627 mutex_lock(&par->open_lock);
1629 if (par->open_count == 1) {
1630 savage_set_default_par(par, &par->initial);
1631 restore_vga(&par->vgastate);
1634 par->open_count--;
1635 mutex_unlock(&par->open_lock);
1680 static void savage_enable_mmio(struct savagefb_par *par)
1686 val = vga_in8(0x3c3, par);
1687 vga_out8(0x3c3, val | 0x01, par);
1688 val = vga_in8(0x3cc, par);
1689 vga_out8(0x3c2, val | 0x01, par);
1691 if (par->chip >= S3_SAVAGE4) {
1692 vga_out8(0x3d4, 0x40, par);
1693 val = vga_in8(0x3d5, par);
1694 vga_out8(0x3d5, val | 1, par);
1699 static void savage_disable_mmio(struct savagefb_par *par)
1705 if (par->chip >= S3_SAVAGE4) {
1706 vga_out8(0x3d4, 0x40, par);
1707 val = vga_in8(0x3d5, par);
1708 vga_out8(0x3d5, val | 1, par);
1715 struct savagefb_par *par = info->par;
1718 if (S3_SAVAGE3D_SERIES(par->chip))
1719 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1722 par->mmio.pbase = pci_resource_start(par->pcidev, 0) +
1725 par->mmio.len = SAVAGE_NEWMMIO_REGSIZE;
1727 par->mmio.vbase = ioremap(par->mmio.pbase, par->mmio.len);
1728 if (!par->mmio.vbase) {
1733 par->mmio.vbase);
1735 info->fix.mmio_start = par->mmio.pbase;
1736 info->fix.mmio_len = par->mmio.len;
1738 par->bci_base = (u32 __iomem *)(par->mmio.vbase + BCI_BUFFER_OFFSET);
1739 par->bci_ptr = 0;
1741 savage_enable_mmio(par);
1748 struct savagefb_par *par = info->par;
1751 savage_disable_mmio(par);
1753 if (par->mmio.vbase) {
1754 iounmap(par->mmio.vbase);
1755 par->mmio.vbase = NULL;
1761 struct savagefb_par *par = info->par;
1766 if (S3_SAVAGE3D_SERIES(par->chip))
1771 par->video.pbase = pci_resource_start(par->pcidev, resource);
1772 par->video.len = video_len;
1773 par->video.vbase = ioremap_wc(par->video.pbase, par->video.len);
1775 if (!par->video.vbase) {
1780 "pbase == %x\n", par->video.vbase, par->video.pbase);
1782 info->fix.smem_start = par->video.pbase;
1783 info->fix.smem_len = par->video.len - par->cob_size;
1784 info->screen_base = par->video.vbase;
1785 par->video.wc_cookie = arch_phys_wc_add(par->video.pbase, video_len);
1788 memset_io(par->video.vbase, 0, par->video.len);
1795 struct savagefb_par *par = info->par;
1799 if (par->video.vbase) {
1800 arch_phys_wc_del(par->video.wc_cookie);
1801 iounmap(par->video.vbase);
1802 par->video.vbase = NULL;
1807 static int savage_init_hw(struct savagefb_par *par)
1820 vga_out8(0x3d4, 0x11, par);
1821 tmp = vga_in8(0x3d5, par);
1822 vga_out8(0x3d5, tmp & 0x7f, par);
1825 vga_out16(0x3d4, 0x4838, par);
1826 vga_out16(0x3d4, 0xa039, par);
1827 vga_out16(0x3c4, 0x0608, par);
1829 vga_out8(0x3d4, 0x40, par);
1830 tmp = vga_in8(0x3d5, par);
1831 vga_out8(0x3d5, tmp & ~0x01, par);
1834 vga_out8(0x3d4, 0x38, par);
1835 vga_out8(0x3d5, 0x48, par);
1838 vga_out16(0x3d4, 0x4838, par);
1842 vga_out8(0x3d4, 0x36, par); /* for register CR36 (CONFG_REG1), */
1843 config1 = vga_in8(0x3d5, par); /* get amount of vram installed */
1847 switch (par->chip) {
1859 vga_out8(0x3d4, 0x68, par); /* memory control 1 */
1860 if ((vga_in8(0x3d5, par) & 0xC0) == (0x01 << 6))
1890 vga_out8(0x3d4, 0x66, par);
1891 cr66 = vga_in8(0x3d5, par);
1892 vga_out8(0x3d5, cr66 | 0x02, par);
1895 vga_out8(0x3d4, 0x66, par);
1896 vga_out8(0x3d5, cr66 & ~0x02, par); /* clear reset flag */
1904 vga_out8(0x3d4, 0x3f, par);
1905 cr3f = vga_in8(0x3d5, par);
1906 vga_out8(0x3d5, cr3f | 0x08, par);
1909 vga_out8(0x3d4, 0x3f, par);
1910 vga_out8(0x3d5, cr3f & ~0x08, par); /* clear reset flags */
1914 par->numClocks = 4;
1915 par->clock[0] = 250000;
1916 par->clock[1] = 250000;
1917 par->clock[2] = 220000;
1918 par->clock[3] = 220000;
1921 vga_out8(0x3c4, 0x08, par);
1922 sr8 = vga_in8(0x3c5, par);
1923 vga_out8(0x3c5, 0x06, par);
1924 vga_out8(0x3c4, 0x10, par);
1925 n = vga_in8(0x3c5, par);
1926 vga_out8(0x3c4, 0x11, par);
1927 m = vga_in8(0x3c5, par);
1928 vga_out8(0x3c4, 0x08, par);
1929 vga_out8(0x3c5, sr8, par);
1933 par->MCLK = ((1431818 * (m+2)) / (n1+2) / (1 << n2) + 50) / 100;
1935 par->MCLK);
1940 if (par->chip == S3_SAVAGE4) {
1943 vga_out8(0x3c4, 0x30, par);
1945 vga_out8(0x3c5, vga_in8(0x3c5, par) & ~0x02, par);
1946 sr30 = vga_in8(0x3c5, par);
1953 if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||
1954 S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly)
1955 par->display_type = DISP_LCD;
1956 else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
1957 par->display_type = DISP_DFP;
1959 par->display_type = DISP_CRT;
1963 if (par->display_type == DISP_LCD) {
1964 unsigned char cr6b = VGArCR(0x6b, par);
1966 int panelX = (VGArSEQ(0x61, par) +
1967 ((VGArSEQ(0x66, par) & 0x02) << 7) + 1) * 8;
1968 int panelY = (VGArSEQ(0x69, par) +
1969 ((VGArSEQ(0x6e, par) & 0x70) << 4) + 1);
1991 if ((VGArSEQ(0x39, par) & 0x03) == 0) {
1993 } else if ((VGArSEQ(0x30, par) & 0x01) == 0) {
2012 par->SavagePanelWidth = panelX;
2013 par->SavagePanelHeight = panelY;
2016 par->display_type = DISP_CRT;
2019 savage_get_default_par(par, &par->state);
2020 par->save = par->state;
2022 if (S3_SAVAGE4_SERIES(par->chip)) {
2027 par->cob_index = 2;
2028 par->cob_size = 0x8000 << par->cob_index;
2029 par->cob_offset = videoRambytes;
2033 par->cob_index = 7;
2034 par->cob_size = 0x400 << par->cob_index;
2035 par->cob_offset = videoRambytes - par->cob_size;
2044 struct savagefb_par *par = info->par;
2047 par->pcidev = dev;
2057 par->chip = S3_SUPERSAVAGE;
2061 par->chip = S3_SAVAGE4;
2065 par->chip = S3_SAVAGE3D;
2069 par->chip = S3_SAVAGE3D;
2073 par->chip = S3_SAVAGE2000;
2077 par->chip = S3_SAVAGE_MX;
2081 par->chip = S3_SAVAGE_MX;
2085 par->chip = S3_SAVAGE_MX;
2089 par->chip = S3_SAVAGE_MX;
2093 par->chip = S3_PROSAVAGE;
2097 par->chip = S3_PROSAVAGE;
2101 par->chip = S3_TWISTER;
2105 par->chip = S3_TWISTER;
2109 par->chip = S3_PROSAVAGEDDR;
2113 par->chip = S3_PROSAVAGEDDR;
2118 if (S3_SAVAGE3D_SERIES(par->chip)) {
2119 par->SavageWaitIdle = savage3D_waitidle;
2120 par->SavageWaitFifo = savage3D_waitfifo;
2121 } else if (S3_SAVAGE4_SERIES(par->chip) ||
2122 S3_SUPERSAVAGE == par->chip) {
2123 par->SavageWaitIdle = savage4_waitidle;
2124 par->SavageWaitFifo = savage4_waitfifo;
2126 par->SavageWaitIdle = savage2000_waitidle;
2127 par->SavageWaitFifo = savage2000_waitfifo;
2141 info->pseudo_palette = par->pseudo_palette;
2171 struct savagefb_par *par;
2181 par = info->par;
2182 mutex_init(&par->open_lock);
2201 video_len = savage_init_hw(par);
2215 savagefb_probe_i2c_connector(info, &par->edid);
2216 fb_edid_to_monspecs(par->edid, &info->monspecs);
2217 kfree(par->edid);
2224 if (par->SavagePanelWidth) {
2228 cvt_mode.xres = par->SavagePanelWidth;
2229 cvt_mode.yres = par->SavagePanelHeight;
2356 struct savagefb_par *par = info->par;
2362 par->pm_state = mesg.event;
2379 savage_set_default_par(par, &par->save);
2380 savage_disable_mmio(par);
2404 struct savagefb_par *par = info->par;
2405 int cur_state = par->pm_state;
2409 par->pm_state = PM_EVENT_ON;
2420 savage_enable_mmio(par);
2421 savage_init_hw(par);