Lines Matching refs:vgabase
196 return vga_rcrt(par->state.vgabase, DDC_REG);
204 vga_wcrt(par->state.vgabase, DDC_REG, val);
271 /* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
275 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
277 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
279 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
316 svga_tilecursor(par->state.vgabase, info, cursor);
473 regval = vga_r(par->state.vgabase, VGA_MIS_R);
474 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
483 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
484 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
486 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5));
487 vga_wseq(par->state.vgabase, 0x13, m - 2);
492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */
493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5));
495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5));
507 void __iomem *vgabase = par->state.vgabase;
510 par->state.vgabase = vgabase;
642 vga_wcrt(par->state.vgabase, 0x38, 0x48);
643 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
644 vga_wseq(par->state.vgabase, 0x08, 0x06);
645 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80);
648 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
649 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80);
652 svga_set_default_gfx_regs(par->state.vgabase);
653 svga_set_default_atc_regs(par->state.vgabase);
654 svga_set_default_seq_regs(par->state.vgabase);
655 svga_set_default_crt_regs(par->state.vgabase);
656 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF);
657 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0);
660 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */
661 svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
663 /* svga_wcrt_mask(par->state.vgabase, 0x33, 0x08, 0x08); */ /* DDR ? */
664 /* svga_wcrt_mask(par->state.vgabase, 0x43, 0x01, 0x01); */ /* DDR ? */
665 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */
666 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */
668 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */
670 /* svga_wcrt_mask(par->state.vgabase, 0x58, 0x03, 0x03); */
672 /* svga_wcrt_mask(par->state.vgabase, 0x53, 0x12, 0x13); */ /* enable MMIO */
673 /* svga_wcrt_mask(par->state.vgabase, 0x40, 0x08, 0x08); */ /* enable write buffer */
678 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value);
686 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
687 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
688 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
689 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */
692 vga_wcrt(par->state.vgabase, 0x3A, 0x35);
693 svga_wattr(par->state.vgabase, 0x33, 0x00);
696 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80);
698 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80);
701 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20);
703 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20);
706 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01);
708 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C);
714 vga_wcrt(par->state.vgabase, 0x86, 0x80);
715 vga_wcrt(par->state.vgabase, 0x90, 0x00);
720 vga_wcrt(par->state.vgabase, 0x50, 0x00);
721 vga_wcrt(par->state.vgabase, 0x67, 0x50);
723 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09);
724 vga_wcrt(par->state.vgabase, 0x66, 0x90);
737 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
738 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
740 vga_wcrt(par->state.vgabase, 0x66, 0x81);
749 vga_wcrt(par->state.vgabase, 0x34, 0x00);
751 vga_wcrt(par->state.vgabase, 0x34, 0x10);
753 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40);
761 svga_set_textmode_vga_regs(par->state.vgabase);
764 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
765 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
768 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
772 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40);
777 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40);
780 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
781 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
784 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
790 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
791 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
794 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30);
798 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30);
806 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
808 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
816 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
820 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
822 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
825 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0);
829 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
830 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0);
844 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
846 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
848 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
850 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
853 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0);
857 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30);
858 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0);
871 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
875 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30);
876 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0);
884 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
885 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
889 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1,
897 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2);
903 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value);
909 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80);
910 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
985 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
986 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
990 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06);
991 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
995 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06);
996 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1000 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06);
1001 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1005 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06);
1006 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
1033 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset);
1064 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30);
1065 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e);
1066 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f);
1081 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1090 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f);
1099 switch (vga_rcrt(par->state.vgabase, 0x2f)) {
1174 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start;
1177 cr38 = vga_rcrt(par->state.vgabase, 0x38);
1178 cr39 = vga_rcrt(par->state.vgabase, 0x39);
1179 vga_wseq(par->state.vgabase, 0x08, 0x06);
1180 vga_wcrt(par->state.vgabase, 0x38, 0x48);
1181 vga_wcrt(par->state.vgabase, 0x39, 0xA5);
1185 par->rev = vga_rcrt(par->state.vgabase, 0x2f);
1191 regval = vga_rcrt(par->state.vgabase, 0x36);
1234 regval = vga_rcrt(par->state.vgabase, 0x37);
1248 regval = vga_rseq(par->state.vgabase, 0x10);
1249 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
1253 vga_wcrt(par->state.vgabase, 0x38, cr38);
1254 vga_wcrt(par->state.vgabase, 0x39, cr39);
1271 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
1349 vga_rcrt(par->state.vgabase, 0x2d),
1350 vga_rcrt(par->state.vgabase, 0x2e),
1351 vga_rcrt(par->state.vgabase, 0x2f),
1352 vga_rcrt(par->state.vgabase, 0x30));