Lines Matching defs:sfb
243 struct s3c_fb *sfb = win->parent;
245 dev_dbg(sfb->dev, "checking parameters\n");
251 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
265 if (sfb->variant.palette[win->index] != 0) {
328 dev_err(sfb->dev, "invalid bpp\n");
332 dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
338 * @sfb: The hardware state.
344 static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
350 if (sfb->variant.has_clksel)
351 clk = clk_get_rate(sfb->bus_clk);
353 clk = clk_get_rate(sfb->lcd_clk);
361 dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
394 struct s3c_fb *sfb = win->parent;
398 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
410 struct s3c_fb *sfb = win->parent;
413 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
424 struct s3c_fb *sfb = win->parent;
428 if (sfb->variant.has_prtcon) {
429 writel(PRTCON_PROTECT, sfb->regs + PRTCON);
430 } else if (sfb->variant.has_shadowcon) {
431 reg = readl(sfb->regs + SHADOWCON);
433 sfb->regs + SHADOWCON);
436 if (sfb->variant.has_prtcon) {
437 writel(0, sfb->regs + PRTCON);
438 } else if (sfb->variant.has_shadowcon) {
439 reg = readl(sfb->regs + SHADOWCON);
441 sfb->regs + SHADOWCON);
448 * @sfb: The main framebuffer state.
451 static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
453 u32 vidcon0 = readl(sfb->regs + VIDCON0);
455 if (enable && !sfb->output_on)
456 pm_runtime_get_sync(sfb->dev);
471 writel(vidcon0, sfb->regs + VIDCON0);
473 if (!enable && sfb->output_on)
474 pm_runtime_put_sync(sfb->dev);
476 sfb->output_on = enable;
489 struct s3c_fb *sfb = win->parent;
490 void __iomem *regs = sfb->regs;
497 dev_dbg(sfb->dev, "setting framebuffer parameters\n");
499 pm_runtime_get_sync(sfb->dev);
532 if (!sfb->output_on)
533 s3c_fb_enable(sfb, 1);
540 writel(info->fix.smem_start, buf + sfb->variant.buf_start);
543 writel(data, buf + sfb->variant.buf_end);
550 writel(data, regs + sfb->variant.buf_size + (win_no * 4));
556 writel(data, regs + VIDOSD_A(win_no, sfb->variant));
565 writel(data, regs + VIDOSD_B(win_no, sfb->variant));
577 if (sfb->variant.has_shadowcon) {
578 data = readl(sfb->regs + SHADOWCON);
580 writel(data, sfb->regs + SHADOWCON);
584 sfb->enabled |= (1 << win->index);
647 void __iomem *keycon = regs + sfb->variant.keycon;
661 writel(data, regs + sfb->variant.wincon + (win_no * 4));
662 writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
665 if (sfb->variant.has_blendcon) {
666 data = readl(sfb->regs + BLENDCON);
672 writel(data, sfb->regs + BLENDCON);
677 pm_runtime_put_sync(sfb->dev);
684 * @sfb: The hardware information.
696 static void s3c_fb_update_palette(struct s3c_fb *sfb,
704 palreg = sfb->regs + sfb->variant.palette[win->index];
706 dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
711 palcon = readl(sfb->regs + WPALCON);
712 writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
719 writel(palcon, sfb->regs + WPALCON);
744 struct s3c_fb *sfb = win->parent;
747 dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
750 pm_runtime_get_sync(sfb->dev);
773 s3c_fb_update_palette(sfb, win, regno, val);
779 pm_runtime_put_sync(sfb->dev);
783 pm_runtime_put_sync(sfb->dev);
797 struct s3c_fb *sfb = win->parent;
800 u32 output_on = sfb->output_on;
802 dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
804 pm_runtime_get_sync(sfb->dev);
806 wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
811 sfb->enabled &= ~(1 << index);
818 sfb->regs + sfb->variant.winmap + (index * 4));
824 writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
827 sfb->enabled |= (1 << index);
833 pm_runtime_put_sync(sfb->dev);
838 writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
845 s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
848 pm_runtime_put_sync(sfb->dev);
850 return output_on == sfb->output_on;
868 struct s3c_fb *sfb = win->parent;
869 void __iomem *buf = sfb->regs + win->index * 8;
872 pm_runtime_get_sync(sfb->dev);
891 dev_err(sfb->dev, "invalid bpp\n");
892 pm_runtime_put_sync(sfb->dev);
903 writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
904 writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
908 pm_runtime_put_sync(sfb->dev);
914 * @sfb: main hardware state
916 static void s3c_fb_enable_irq(struct s3c_fb *sfb)
918 void __iomem *regs = sfb->regs;
921 if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
939 * @sfb: main hardware state
941 static void s3c_fb_disable_irq(struct s3c_fb *sfb)
943 void __iomem *regs = sfb->regs;
946 if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
959 struct s3c_fb *sfb = dev_id;
960 void __iomem *regs = sfb->regs;
963 spin_lock(&sfb->slock);
972 sfb->vsync_info.count++;
973 wake_up_interruptible(&sfb->vsync_info.wait);
979 s3c_fb_disable_irq(sfb);
981 spin_unlock(&sfb->slock);
987 * @sfb: main hardware state
990 static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
998 pm_runtime_get_sync(sfb->dev);
1000 count = sfb->vsync_info.count;
1001 s3c_fb_enable_irq(sfb);
1002 ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
1003 count != sfb->vsync_info.count,
1006 pm_runtime_put_sync(sfb->dev);
1018 struct s3c_fb *sfb = win->parent;
1029 ret = s3c_fb_wait_for_vsync(sfb, crtc);
1075 * @sfb: The base resources for the hardware.
1080 static int s3c_fb_alloc_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1087 dev_dbg(sfb->dev, "allocating memory for display\n");
1092 dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1103 dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1105 fbi->screen_buffer = dma_alloc_wc(sfb->dev, size, &map_dma, GFP_KERNEL);
1109 dev_dbg(sfb->dev, "mapped %x to %p\n",
1120 * @sfb: The base resources for the hardware.
1125 static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1130 dma_free_wc(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1141 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1146 if (sfb->variant.has_shadowcon) {
1147 data = readl(sfb->regs + SHADOWCON);
1150 writel(data, sfb->regs + SHADOWCON);
1155 s3c_fb_free_memory(sfb, win);
1162 * @sfb: The base resources for the hardware
1169 static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1181 dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1183 init_waitqueue_head(&sfb->vsync_info.wait);
1188 palette_size * sizeof(u32), sfb->dev);
1192 windata = sfb->pdata->win[win_no];
1193 initmode = *sfb->pdata->vtiming;
1204 win->parent = sfb;
1209 ret = s3c_fb_alloc_memory(sfb, win);
1211 dev_err(sfb->dev, "failed to allocate display memory\n");
1253 dev_err(sfb->dev, "check_var failed on initial video params\n");
1263 dev_err(sfb->dev, "failed to allocate fb cmap\n");
1267 dev_dbg(sfb->dev, "about to register framebuffer\n");
1273 dev_err(sfb->dev, "failed to register framebuffer\n");
1277 dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1284 * @sfb: The base resources for the hardware.
1288 static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)
1290 struct fb_videomode *vmode = sfb->pdata->vtiming;
1291 void __iomem *regs = sfb->regs;
1298 clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);
1300 data = sfb->pdata->vidcon0;
1308 if (sfb->variant.is_2443)
1315 writel(data, regs + sfb->variant.vidtcon);
1320 writel(data, regs + sfb->variant.vidtcon + 4);
1326 writel(data, regs + sfb->variant.vidtcon + 8);
1331 * @sfb: The base resources for the hardware.
1336 static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1338 void __iomem *regs = sfb->regs;
1341 writel(0, regs + sfb->variant.wincon + (win * 4));
1342 writel(0, regs + VIDOSD_A(win, sfb->variant));
1343 writel(0, regs + VIDOSD_B(win, sfb->variant));
1344 writel(0, regs + VIDOSD_C(win, sfb->variant));
1346 if (sfb->variant.has_shadowcon) {
1347 reg = readl(sfb->regs + SHADOWCON);
1351 writel(reg, sfb->regs + SHADOWCON);
1361 struct s3c_fb *sfb;
1381 sfb = devm_kzalloc(dev, sizeof(*sfb), GFP_KERNEL);
1382 if (!sfb)
1385 dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1387 sfb->dev = dev;
1388 sfb->pdata = pd;
1389 sfb->variant = fbdrv->variant;
1391 spin_lock_init(&sfb->slock);
1393 sfb->bus_clk = devm_clk_get(dev, "lcd");
1394 if (IS_ERR(sfb->bus_clk)) {
1396 return PTR_ERR(sfb->bus_clk);
1399 clk_prepare_enable(sfb->bus_clk);
1401 if (!sfb->variant.has_clksel) {
1402 sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1403 if (IS_ERR(sfb->lcd_clk)) {
1405 ret = PTR_ERR(sfb->lcd_clk);
1409 clk_prepare_enable(sfb->lcd_clk);
1412 pm_runtime_enable(sfb->dev);
1414 sfb->regs = devm_platform_ioremap_resource(pdev, 0);
1415 if (IS_ERR(sfb->regs)) {
1416 ret = PTR_ERR(sfb->regs);
1426 sfb->irq_no = res->start;
1427 ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq,
1428 0, "s3c_fb", sfb);
1434 dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1436 platform_set_drvdata(pdev, sfb);
1437 pm_runtime_get_sync(sfb->dev);
1443 writel(pd->vidcon1, sfb->regs + VIDCON1);
1446 if (sfb->variant.has_fixvclk) {
1447 reg = readl(sfb->regs + VIDCON1);
1450 writel(reg, sfb->regs + VIDCON1);
1456 s3c_fb_clear_win(sfb, win);
1460 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1467 s3c_fb_set_rgb_timing(sfb);
1475 ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1476 &sfb->windows[win]);
1480 s3c_fb_release_win(sfb, sfb->windows[win]);
1485 platform_set_drvdata(pdev, sfb);
1486 pm_runtime_put_sync(sfb->dev);
1491 pm_runtime_put_sync(sfb->dev);
1494 pm_runtime_disable(sfb->dev);
1496 if (!sfb->variant.has_clksel)
1497 clk_disable_unprepare(sfb->lcd_clk);
1500 clk_disable_unprepare(sfb->bus_clk);
1514 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1517 pm_runtime_get_sync(sfb->dev);
1520 if (sfb->windows[win])
1521 s3c_fb_release_win(sfb, sfb->windows[win]);
1523 if (!sfb->variant.has_clksel)
1524 clk_disable_unprepare(sfb->lcd_clk);
1526 clk_disable_unprepare(sfb->bus_clk);
1528 pm_runtime_put_sync(sfb->dev);
1529 pm_runtime_disable(sfb->dev);
1537 struct s3c_fb *sfb = dev_get_drvdata(dev);
1541 pm_runtime_get_sync(sfb->dev);
1544 win = sfb->windows[win_no];
1552 if (!sfb->variant.has_clksel)
1553 clk_disable_unprepare(sfb->lcd_clk);
1555 clk_disable_unprepare(sfb->bus_clk);
1557 pm_runtime_put_sync(sfb->dev);
1564 struct s3c_fb *sfb = dev_get_drvdata(dev);
1565 struct s3c_fb_platdata *pd = sfb->pdata;
1570 pm_runtime_get_sync(sfb->dev);
1572 clk_prepare_enable(sfb->bus_clk);
1574 if (!sfb->variant.has_clksel)
1575 clk_prepare_enable(sfb->lcd_clk);
1579 writel(pd->vidcon1, sfb->regs + VIDCON1);
1582 if (sfb->variant.has_fixvclk) {
1583 reg = readl(sfb->regs + VIDCON1);
1586 writel(reg, sfb->regs + VIDCON1);
1590 for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1591 s3c_fb_clear_win(sfb, win_no);
1593 for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1594 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1595 win = sfb->windows[win_no];
1606 s3c_fb_set_rgb_timing(sfb);
1610 win = sfb->windows[win_no];
1618 pm_runtime_put_sync(sfb->dev);
1627 struct s3c_fb *sfb = dev_get_drvdata(dev);
1629 if (!sfb->variant.has_clksel)
1630 clk_disable_unprepare(sfb->lcd_clk);
1632 clk_disable_unprepare(sfb->bus_clk);
1639 struct s3c_fb *sfb = dev_get_drvdata(dev);
1640 struct s3c_fb_platdata *pd = sfb->pdata;
1642 clk_prepare_enable(sfb->bus_clk);
1644 if (!sfb->variant.has_clksel)
1645 clk_prepare_enable(sfb->lcd_clk);
1649 writel(pd->vidcon1, sfb->regs + VIDCON1);