Lines Matching refs:chip
62 RIVA_HW_INST *chip
65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01);
70 RIVA_HW_INST *chip
73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
78 RIVA_HW_INST *chip
81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) ||
82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01);
87 RIVA_HW_INST *chip,
92 VGA_WR08(chip->PCIO, 0x3D4, 0x11);
93 cr11 = VGA_RD08(chip->PCIO, 0x3D5);
96 VGA_WR08(chip->PCIO, 0x3D5, cr11);
100 RIVA_HW_INST *chip,
104 VGA_WR08(chip->PVIO, 0x3C4, 0x06);
105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
106 vgaLockUnlock(chip, Lock);
110 RIVA_HW_INST *chip,
114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
116 vgaLockUnlock(chip, Lock);
121 RIVA_HW_INST *chip,
126 cursor = chip->CurrentState->cursor1;
127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) |
129 VGA_WR08(chip->PCIO, 0x3D4, 0x31);
130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1);
614 RIVA_HW_INST *chip
621 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
623 MClk = (N * chip->CrystalFreqKHz / M) >> P;
628 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
803 RIVA_HW_INST *chip
810 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
812 MClk = (N * chip->CrystalFreqKHz / M) >> P;
813 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
815 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
816 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
820 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1066 RIVA_HW_INST *chip
1073 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0);
1075 MClk = (N * chip->CrystalFreqKHz / M) >> P;
1076 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1078 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1079 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0);
1083 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ?
1085 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ?
1111 RIVA_HW_INST *chip,
1130 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0);
1132 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1177 RIVA_HW_INST *chip
1189 if (chip->CrystalFreqKHz == 13500)
1192 highM = 13 - (chip->Architecture == NV_ARCH_03);
1197 highM = 14 - (chip->Architecture == NV_ARCH_03);
1200 highP = 4 - (chip->Architecture == NV_ARCH_03);
1204 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz))
1208 N = (VClk << P) * M / chip->CrystalFreqKHz;
1210 Freq = (chip->CrystalFreqKHz * N / M) >> P;
1237 RIVA_HW_INST *chip,
1260 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip))
1263 switch (chip->Architecture)
1270 chip);
1286 chip);
1298 if((chip->Chipset == NV_CHIP_IGEFORCE2) ||
1299 (chip->Chipset == NV_CHIP_0x01F0))
1305 chip, pdev);
1311 chip);
1313 state->cursor0 = 0x80 | (chip->CursorStart >> 17);
1314 state->cursor1 = (chip->CursorStart >> 11) << 2;
1315 state->cursor2 = chip->CursorStart >> 24;
1317 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0);
1325 if((bpp != 8) && (chip->Architecture != NV_ARCH_03))
1347 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1])
1350 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1])
1353 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1])
1356 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1])
1359 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1])
1363 RIVA_HW_INST *chip
1368 switch (chip->Architecture)
1372 chip->Tri03 = NULL;
1373 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1383 chip->Tri03 = NULL;
1384 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]);
1390 RIVA_HW_INST *chip,
1401 switch (chip->Architecture)
1407 NV_WR32(chip->PFB, 0x00000200, state->config);
1417 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1423 chip->Tri03 = NULL;
1429 chip->Tri03 = NULL;
1433 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03);
1434 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0);
1435 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1);
1436 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2);
1437 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3);
1438 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0);
1439 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1);
1440 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2);
1441 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3);
1447 NV_WR32(chip->PFB, 0x00000200, state->config);
1456 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1461 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1467 chip->Tri03 = NULL;
1473 chip->Tri03 = NULL;
1476 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1477 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1478 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1479 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1480 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1481 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1482 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1483 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1488 if(chip->twoHeads) {
1489 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1490 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
1491 chip->LockUnlock(chip, 0);
1502 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1507 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);
1513 chip->Tri03 = NULL;
1519 chip->Tri03 = NULL;
1523 if(chip->Architecture == NV_ARCH_10) {
1524 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1525 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1526 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1527 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1528 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1529 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1530 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1531 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1532 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3);
1534 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0);
1535 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1);
1536 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2);
1537 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3);
1538 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0);
1539 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1);
1540 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2);
1541 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3);
1542 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3);
1543 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3);
1544 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200));
1545 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204));
1547 if(chip->twoHeads) {
1548 NV_WR32(chip->PCRTC0, 0x00000860, state->head);
1549 NV_WR32(chip->PCRTC0, 0x00002860, state->head2);
1551 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25));
1553 NV_WR32(chip->PMC, 0x00008704, 1);
1554 NV_WR32(chip->PMC, 0x00008140, 0);
1555 NV_WR32(chip->PMC, 0x00008920, 0);
1556 NV_WR32(chip->PMC, 0x00008924, 0);
1557 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff);
1558 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff);
1559 NV_WR32(chip->PMC, 0x00001588, 0);
1561 NV_WR32(chip->PFB, 0x00000240, 0);
1562 NV_WR32(chip->PFB, 0x00000250, 0);
1563 NV_WR32(chip->PFB, 0x00000260, 0);
1564 NV_WR32(chip->PFB, 0x00000270, 0);
1565 NV_WR32(chip->PFB, 0x00000280, 0);
1566 NV_WR32(chip->PFB, 0x00000290, 0);
1567 NV_WR32(chip->PFB, 0x000002A0, 0);
1568 NV_WR32(chip->PFB, 0x000002B0, 0);
1570 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240));
1571 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244));
1572 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248));
1573 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C));
1574 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250));
1575 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254));
1576 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258));
1577 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C));
1578 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260));
1579 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264));
1580 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268));
1581 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C));
1582 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270));
1583 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274));
1584 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278));
1585 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C));
1586 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280));
1587 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284));
1588 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288));
1589 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C));
1590 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290));
1591 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294));
1592 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298));
1593 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C));
1594 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0));
1595 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4));
1596 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8));
1597 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC));
1598 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0));
1599 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4));
1600 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8));
1601 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC));
1602 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000);
1603 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000);
1604 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1605 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008);
1606 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200);
1608 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1609 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1610 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800);
1613 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1614 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000);
1615 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004);
1616 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400);
1618 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1619 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800);
1621 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1622 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00);
1624 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1625 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000);
1627 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1628 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400);
1630 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1631 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800);
1633 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1634 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400);
1636 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1637 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000);
1639 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1640 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040);
1642 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000);
1644 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig);
1646 if(chip->flatPanel) {
1647 if((chip->Chipset & 0x0ff0) == 0x0110) {
1648 NV_WR32(chip->PRAMDAC, 0x0528, state->dither);
1650 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1651 NV_WR32(chip->PRAMDAC, 0x083C, state->dither);
1654 VGA_WR08(chip->PCIO, 0x03D4, 0x53);
1655 VGA_WR08(chip->PCIO, 0x03D5, 0);
1656 VGA_WR08(chip->PCIO, 0x03D4, 0x54);
1657 VGA_WR08(chip->PCIO, 0x03D5, 0);
1658 VGA_WR08(chip->PCIO, 0x03D4, 0x21);
1659 VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
1662 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1663 VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1666 UpdateFifoState(chip);
1670 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1671 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
1672 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1673 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
1674 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1675 VGA_WR08(chip->PCIO, 0x03D5, state->screen);
1676 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1677 VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
1678 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1679 VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
1680 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1681 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
1682 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1683 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
1684 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1685 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
1686 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1687 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
1688 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1689 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
1690 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1691 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1693 if(!chip->flatPanel) {
1694 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);
1695 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel);
1696 if(chip->twoHeads)
1697 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2);
1699 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale);
1701 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general);
1706 NV_WR32(chip->PCRTC, 0x00000140, 0);
1707 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit);
1711 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01);
1715 chip->CurrentState = state;
1719 chip->FifoFreeCount = 0;
1721 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0);
1725 RIVA_HW_INST *chip,
1732 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1733 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
1734 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1735 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
1736 VGA_WR08(chip->PCIO, 0x03D4, 0x25);
1737 state->screen = VGA_RD08(chip->PCIO, 0x03D5);
1738 VGA_WR08(chip->PCIO, 0x03D4, 0x28);
1739 state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
1740 VGA_WR08(chip->PCIO, 0x03D4, 0x2D);
1741 state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
1742 VGA_WR08(chip->PCIO, 0x03D4, 0x1B);
1743 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
1744 VGA_WR08(chip->PCIO, 0x03D4, 0x20);
1745 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
1746 VGA_WR08(chip->PCIO, 0x03D4, 0x30);
1747 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
1748 VGA_WR08(chip->PCIO, 0x03D4, 0x31);
1749 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
1750 VGA_WR08(chip->PCIO, 0x03D4, 0x2F);
1751 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
1752 VGA_WR08(chip->PCIO, 0x03D4, 0x39);
1753 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1754 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508);
1755 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520);
1756 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C);
1757 state->general = NV_RD32(chip->PRAMDAC, 0x00000600);
1758 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848);
1759 state->config = NV_RD32(chip->PFB, 0x00000200);
1760 switch (chip->Architecture)
1763 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630);
1764 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634);
1765 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638);
1766 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C);
1767 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650);
1768 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654);
1769 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658);
1770 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C);
1773 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1774 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1775 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1776 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1777 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1778 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1779 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1780 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1785 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1786 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1787 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1788 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1789 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1790 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1791 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1792 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1793 if(chip->twoHeads) {
1794 state->head = NV_RD32(chip->PCRTC0, 0x00000860);
1795 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860);
1796 VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1797 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
1799 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1800 state->extra = VGA_RD08(chip->PCIO, 0x03D5);
1801 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810);
1803 if((chip->Chipset & 0x0ff0) == 0x0110) {
1804 state->dither = NV_RD32(chip->PRAMDAC, 0x0528);
1806 if((chip->Chipset & 0x0ff0) >= 0x0170) {
1807 state->dither = NV_RD32(chip->PRAMDAC, 0x083C);
1814 RIVA_HW_INST *chip,
1818 NV_WR32(chip->PCRTC, 0x800, start);
1823 RIVA_HW_INST *chip,
1834 chip->LockUnlock(chip, 0);
1838 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset);
1840 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset);
1842 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1843 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F));
1844 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5);
1845 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60));
1849 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A);
1850 VGA_WR08(chip->PCIO, 0x3C0, 0x13);
1851 VGA_WR08(chip->PCIO, 0x3C0, pan);
1855 RIVA_HW_INST *chip,
1861 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1863 RIVA_FIFO_FREE(*chip,Tri03,5);
1864 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1866 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1868 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1872 RIVA_HW_INST *chip,
1878 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1880 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1882 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1884 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1888 RIVA_HW_INST *chip,
1894 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1896 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003);
1898 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004);
1900 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1904 RIVA_HW_INST *chip,
1910 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1912 RIVA_FIFO_FREE(*chip,Tri03,5);
1913 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1915 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1917 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013);
1921 RIVA_HW_INST *chip,
1927 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]);
1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005);
1931 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006);
1933 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1937 RIVA_HW_INST *chip,
1943 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]);
1945 RIVA_FIFO_FREE(*chip,Tri03,4);
1946 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007);
1949 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014);
1960 RIVA_HW_INST *chip
1964 * Fill in chip configuration.
1966 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020)
1968 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
1969 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02))
1974 chip->RamBandwidthKBytesPerSec = 800000;
1975 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03)
1978 chip->RamAmountKBytes = 1024 * 4;
1981 chip->RamAmountKBytes = 1024 * 2;
1984 chip->RamAmountKBytes = 1024 * 8;
1990 chip->RamBandwidthKBytesPerSec = 1000000;
1991 chip->RamAmountKBytes = 1024 * 8;
1999 chip->RamBandwidthKBytesPerSec = 1000000;
2000 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2003 chip->RamAmountKBytes = 1024 * 8;
2006 chip->RamAmountKBytes = 1024 * 4;
2009 chip->RamAmountKBytes = 1024 * 2;
2013 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2014 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
2015 chip->VBlankBit = 0x00000100;
2016 chip->MaxVClockFreqKHz = 256000;
2018 * Set chip functions.
2020 chip->Busy = nv3Busy;
2021 chip->ShowHideCursor = ShowHideCursor;
2022 chip->LoadStateExt = LoadStateExt;
2023 chip->UnloadStateExt = UnloadStateExt;
2024 chip->SetStartAddress = SetStartAddress3;
2025 chip->SetSurfaces2D = nv3SetSurfaces2D;
2026 chip->SetSurfaces3D = nv3SetSurfaces3D;
2027 chip->LockUnlock = nv3LockUnlock;
2031 RIVA_HW_INST *chip
2035 * Fill in chip configuration.
2037 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100)
2039 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2
2044 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003)
2047 chip->RamAmountKBytes = 1024 * 32;
2050 chip->RamAmountKBytes = 1024 * 4;
2053 chip->RamAmountKBytes = 1024 * 8;
2057 chip->RamAmountKBytes = 1024 * 16;
2061 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2064 chip->RamBandwidthKBytesPerSec = 800000;
2067 chip->RamBandwidthKBytesPerSec = 1000000;
2070 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500;
2071 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
2072 chip->VBlankBit = 0x00000001;
2073 chip->MaxVClockFreqKHz = 350000;
2075 * Set chip functions.
2077 chip->Busy = nv4Busy;
2078 chip->ShowHideCursor = ShowHideCursor;
2079 chip->LoadStateExt = LoadStateExt;
2080 chip->UnloadStateExt = UnloadStateExt;
2081 chip->SetStartAddress = SetStartAddress;
2082 chip->SetSurfaces2D = nv4SetSurfaces2D;
2083 chip->SetSurfaces3D = nv4SetSurfaces3D;
2084 chip->LockUnlock = nv4LockUnlock;
2088 RIVA_HW_INST *chip,
2099 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001))
2100 NV_WR32(chip->PMC, 0x00000004, 0x01000001);
2104 * Fill in chip configuration.
2110 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
2115 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
2117 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF)
2120 chip->RamAmountKBytes = 1024 * 2;
2123 chip->RamAmountKBytes = 1024 * 4;
2126 chip->RamAmountKBytes = 1024 * 8;
2129 chip->RamAmountKBytes = 1024 * 16;
2132 chip->RamAmountKBytes = 1024 * 32;
2135 chip->RamAmountKBytes = 1024 * 64;
2138 chip->RamAmountKBytes = 1024 * 128;
2141 chip->RamAmountKBytes = 1024 * 16;
2145 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003)
2148 chip->RamBandwidthKBytesPerSec = 800000;
2151 chip->RamBandwidthKBytesPerSec = 1000000;
2154 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ?
2168 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22))
2169 chip->CrystalFreqKHz = 27000;
2175 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
2176 chip->CURSOR = NULL; /* can't set this here */
2177 chip->VBlankBit = 0x00000001;
2178 chip->MaxVClockFreqKHz = 350000;
2180 * Set chip functions.
2182 chip->Busy = nv10Busy;
2183 chip->ShowHideCursor = ShowHideCursor;
2184 chip->LoadStateExt = LoadStateExt;
2185 chip->UnloadStateExt = UnloadStateExt;
2186 chip->SetStartAddress = SetStartAddress;
2187 chip->SetSurfaces2D = nv10SetSurfaces2D;
2188 chip->SetSurfaces3D = nv10SetSurfaces3D;
2189 chip->LockUnlock = nv4LockUnlock;
2203 chip->twoHeads = TRUE;
2206 chip->twoHeads = FALSE;
2212 RIVA_HW_INST *chip,
2220 chip->Version = RIVA_SW_VERSION;
2224 switch (chip->Architecture)
2227 nv3GetConfig(chip);
2230 nv4GetConfig(chip);
2235 nv10GetConfig(chip, pdev, chipset);
2240 chip->Chipset = chipset;
2244 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]);
2245 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]);
2246 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]);
2247 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]);
2248 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]);
2249 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]);
2250 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]);
2251 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]);