Lines Matching defs:state
242 static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
273 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
277 if (state->enable_mp)
285 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
290 if (!state->gr_during_vid && ainfo->vid_en)
340 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
344 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz;
356 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ;
360 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz;
370 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz;
381 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz;
388 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz;
427 static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
433 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5;
435 if (state->mem_aligned) gmisses = 2;
438 eburst_size = state->memory_width * 1;
440 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz;
451 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz;
452 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0;
459 nv3_iterate(res_info, state,ainfo);
461 if (state->enable_mp)
463 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
464 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000;
471 nv3_iterate(res_info, state,ainfo);
478 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
481 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0;
483 nv3_iterate(res_info, state,ainfo);
490 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz;
493 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ;
495 nv3_iterate(res_info, state, ainfo);
533 static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo)
547 done = nv3_arb(res_info, state,ainfo);
563 nv3_sim_state * state
571 ainfo.vid_en = state->enable_video;
574 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
575 ainfo.vdrain_rate = (int) state->pclk_khz * 2;
576 if (state->video_scale != 0)
577 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale;
580 if (!state->gr_during_vid && state->enable_video)
585 res_vid = nv3_get_param(res_info, state, &ainfo);
592 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8);
594 res_gr = nv3_get_param(res_info, state, &ainfo);
604 res_gr = nv3_get_param(res_info, state, &ainfo);
1233 * mode state structure.
1238 RIVA_HW_STATE *state,
1253 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */
1254 state->width = width;
1255 state->height = height;
1268 &(state->arbitration0),
1269 &(state->arbitration1),
1271 state->cursor0 = 0x00;
1272 state->cursor1 = 0x78;
1273 state->cursor2 = 0x00000000;
1274 state->pllsel = 0x10010100;
1275 state->config = ((width + 31)/32)
1278 state->general = 0x00100100;
1279 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02;
1284 &(state->arbitration0),
1285 &(state->arbitration1),
1287 state->cursor0 = 0x00;
1288 state->cursor1 = 0xFC;
1289 state->cursor2 = 0x00000000;
1290 state->pllsel = 0x10000700;
1291 state->config = 0x00001114;
1292 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1293 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1303 &(state->arbitration0),
1304 &(state->arbitration1),
1309 &(state->arbitration0),
1310 &(state->arbitration1),
1313 state->cursor0 = 0x80 | (chip->CursorStart >> 17);
1314 state->cursor1 = (chip->CursorStart >> 11) << 2;
1315 state->cursor2 = chip->CursorStart >> 24;
1316 state->pllsel = 0x10000700;
1317 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0);
1318 state->general = bpp == 16 ? 0x00101100 : 0x00100100;
1319 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00;
1326 state->general |= 0x00000030;
1328 state->vpll = (p << 16) | (n << 8) | m;
1329 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3;
1330 state->pixel = pixelDepth > 2 ? 3 : pixelDepth;
1331 state->offset0 =
1332 state->offset1 =
1333 state->offset2 =
1334 state->offset3 = 0;
1335 state->pitch0 =
1336 state->pitch1 =
1337 state->pitch2 =
1338 state->pitch3 = pixelDepth * width;
1343 * Load fixed function state and pre-calculated/stored state.
1379 * Initialize state for the RivaTriangle3D05 routines.
1391 RIVA_HW_STATE *state
1397 * Load HW fixed function state.
1407 NV_WR32(chip->PFB, 0x00000200, state->config);
1411 switch (state->bpp)
1434 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0);
1435 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1);
1436 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2);
1437 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3);
1438 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0);
1439 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1);
1440 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2);
1441 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3);
1447 NV_WR32(chip->PFB, 0x00000200, state->config);
1451 switch (state->bpp)
1476 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1477 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1478 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1479 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1480 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1481 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1482 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1483 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1490 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
1497 switch (state->bpp)
1524 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0);
1525 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1);
1526 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2);
1527 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3);
1528 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0);
1529 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1);
1530 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2);
1531 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3);
1532 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3);
1534 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0);
1535 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1);
1536 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2);
1537 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3);
1538 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0);
1539 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1);
1540 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2);
1541 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3);
1542 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3);
1543 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3);
1548 NV_WR32(chip->PCRTC0, 0x00000860, state->head);
1549 NV_WR32(chip->PCRTC0, 0x00002860, state->head2);
1644 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig);
1648 NV_WR32(chip->PRAMDAC, 0x0528, state->dither);
1651 NV_WR32(chip->PRAMDAC, 0x083C, state->dither);
1663 VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1668 * Load HW mode state.
1671 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
1673 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1);
1675 VGA_WR08(chip->PCIO, 0x03D5, state->screen);
1677 VGA_WR08(chip->PCIO, 0x03D5, state->pixel);
1679 VGA_WR08(chip->PCIO, 0x03D5, state->horiz);
1681 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0);
1683 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1);
1685 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0);
1687 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1);
1689 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2);
1691 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1694 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll);
1695 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel);
1697 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2);
1699 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale);
1701 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general);
1713 * Set current state pointer.
1715 chip->CurrentState = state;
1726 RIVA_HW_STATE *state
1730 * Save current HW state.
1733 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5);
1735 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5);
1737 state->screen = VGA_RD08(chip->PCIO, 0x03D5);
1739 state->pixel = VGA_RD08(chip->PCIO, 0x03D5);
1741 state->horiz = VGA_RD08(chip->PCIO, 0x03D5);
1743 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5);
1745 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5);
1747 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5);
1749 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5);
1751 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5);
1753 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1754 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508);
1755 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520);
1756 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C);
1757 state->general = NV_RD32(chip->PRAMDAC, 0x00000600);
1758 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848);
1759 state->config = NV_RD32(chip->PFB, 0x00000200);
1763 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630);
1764 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634);
1765 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638);
1766 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C);
1767 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650);
1768 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654);
1769 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658);
1770 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C);
1773 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1774 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1775 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1776 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1777 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1778 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1779 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1780 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1785 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640);
1786 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644);
1787 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648);
1788 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C);
1789 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670);
1790 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674);
1791 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678);
1792 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C);
1794 state->head = NV_RD32(chip->PCRTC0, 0x00000860);
1795 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860);
1797 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
1800 state->extra = VGA_RD08(chip->PCIO, 0x03D5);
1801 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810);
1804 state->dither = NV_RD32(chip->PRAMDAC, 0x0528);
1807 state->dither = NV_RD32(chip->PRAMDAC, 0x083C);