Lines Matching defs:par
271 static int riva_bl_get_level_brightness(struct riva_par *par,
274 struct fb_info *info = pci_get_drvdata(par->pdev);
293 struct riva_par *par = bl_get_data(bd);
303 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
304 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
308 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
310 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
311 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
320 static void riva_bl_init(struct riva_par *par)
323 struct fb_info *info = pci_get_drvdata(par->pdev);
327 if (!par->FlatPanel)
341 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops,
374 static inline void riva_bl_init(struct riva_par *par) {}
384 static inline void CRTCout(struct riva_par *par, unsigned char index,
387 VGA_WR08(par->riva.PCIO, 0x3d4, index);
388 VGA_WR08(par->riva.PCIO, 0x3d5, val);
391 static inline unsigned char CRTCin(struct riva_par *par,
394 VGA_WR08(par->riva.PCIO, 0x3d4, index);
395 return (VGA_RD08(par->riva.PCIO, 0x3d5));
398 static inline void GRAout(struct riva_par *par, unsigned char index,
401 VGA_WR08(par->riva.PVIO, 0x3ce, index);
402 VGA_WR08(par->riva.PVIO, 0x3cf, val);
405 static inline unsigned char GRAin(struct riva_par *par,
408 VGA_WR08(par->riva.PVIO, 0x3ce, index);
409 return (VGA_RD08(par->riva.PVIO, 0x3cf));
412 static inline void SEQout(struct riva_par *par, unsigned char index,
415 VGA_WR08(par->riva.PVIO, 0x3c4, index);
416 VGA_WR08(par->riva.PVIO, 0x3c5, val);
419 static inline unsigned char SEQin(struct riva_par *par,
422 VGA_WR08(par->riva.PVIO, 0x3c4, index);
423 return (VGA_RD08(par->riva.PVIO, 0x3c5));
426 static inline void ATTRout(struct riva_par *par, unsigned char index,
429 VGA_WR08(par->riva.PCIO, 0x3c0, index);
430 VGA_WR08(par->riva.PCIO, 0x3c0, val);
433 static inline unsigned char ATTRin(struct riva_par *par,
436 VGA_WR08(par->riva.PCIO, 0x3c0, index);
437 return (VGA_RD08(par->riva.PCIO, 0x3c1));
440 static inline void MISCout(struct riva_par *par, unsigned char val)
442 VGA_WR08(par->riva.PVIO, 0x3c2, val);
445 static inline unsigned char MISCin(struct riva_par *par)
447 return (VGA_RD08(par->riva.PVIO, 0x3cc));
468 * @par: pointer to private data
483 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
511 writel(tmp, &par->riva.CURSOR[k++]);
574 * @par: pointer to riva_par object containing info for current riva board
584 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
589 par->riva.LockUnlock(&par->riva, 0);
591 par->riva.UnloadStateExt(&par->riva, ®s->ext);
593 regs->misc_output = MISCin(par);
596 regs->crtc[i] = CRTCin(par, i);
599 regs->attr[i] = ATTRin(par, i);
602 regs->gra[i] = GRAin(par, i);
605 regs->seq[i] = SEQin(par, i);
611 * @par: pointer to riva_par object containing info for current riva board
623 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
629 CRTCout(par, 0x11, 0x00);
631 par->riva.LockUnlock(&par->riva, 0);
633 par->riva.LoadStateExt(&par->riva, state);
635 MISCout(par, regs->misc_output);
643 CRTCout(par, i, regs->crtc[i]);
648 ATTRout(par, i, regs->attr[i]);
651 GRAout(par, i, regs->gra[i]);
654 SEQout(par, i, regs->seq[i]);
674 struct riva_par *par = info->par;
711 if (par->FlatPanel) {
767 if (par->riva.Architecture >= NV_ARCH_10)
768 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
779 rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width,
784 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
786 if (par->FlatPanel == 1) {
790 if (par->SecondCRTC) {
791 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
793 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
798 } else if (par->riva.twoHeads) {
799 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
801 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
804 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
806 if (par->FlatPanel == 1) {
811 par->current_state = newmode;
812 riva_load_state(par, &par->current_state);
813 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
947 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
949 RIVA_FIFO_FREE(par->riva, Patt, 4);
950 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
951 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
952 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
953 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
957 static inline void wait_for_idle(struct riva_par *par)
959 while (par->riva.Busy(&par->riva));
966 riva_set_rop_solid(struct riva_par *par, int rop)
968 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
969 RIVA_FIFO_FREE(par->riva, Rop, 1);
970 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
976 struct riva_par *par = info->par;
978 RIVA_FIFO_FREE(par->riva, Clip, 2);
979 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
980 NV_WR32(&par->riva.Clip->WidthHeight, 0,
983 riva_set_rop_solid(par, 0xcc);
984 wait_for_idle(par);
1029 struct riva_par *par = info->par;
1032 mutex_lock(&par->open_lock);
1033 if (!par->ref_count) {
1035 memset(&par->state, 0, sizeof(struct vgastate));
1036 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1038 if (par->riva.Architecture == NV_ARCH_03)
1039 par->state.flags |= VGA_SAVE_CMAP;
1040 save_vga(&par->state);
1043 CRTCout(par, 0x11, 0xFF);
1044 par->riva.LockUnlock(&par->riva, 0);
1046 riva_save_state(par, &par->initial_state);
1048 par->ref_count++;
1049 mutex_unlock(&par->open_lock);
1056 struct riva_par *par = info->par;
1059 mutex_lock(&par->open_lock);
1060 if (!par->ref_count) {
1061 mutex_unlock(&par->open_lock);
1064 if (par->ref_count == 1) {
1065 par->riva.LockUnlock(&par->riva, 0);
1066 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1067 riva_load_state(par, &par->initial_state);
1069 restore_vga(&par->state);
1071 par->riva.LockUnlock(&par->riva, 1);
1073 par->ref_count--;
1074 mutex_unlock(&par->open_lock);
1082 struct riva_par *par = info->par;
1103 if (par->riva.Architecture == NV_ARCH_03)
1189 struct riva_par *par = info->par;
1194 CRTCout(par, 0x11, 0xFF);
1195 par->riva.LockUnlock(&par->riva, 0);
1202 par->cursor_reset = 1;
1233 struct riva_par *par = info->par;
1238 par->riva.SetStartAddress(&par->riva, base);
1245 struct riva_par *par= info->par;
1248 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1249 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1271 SEQout(par, 0x01, tmp);
1272 CRTCout(par, 0x1a, vesa);
1302 struct riva_par *par = info->par;
1303 RIVA_HW_INST *chip = &par->riva;
1324 if (par->riva.Architecture == NV_ARCH_03) {
1327 par->palette[regno] = ((red & 0xf800) >> 1) |
1332 par->palette[regno] = ((red & 0xff00) << 8) |
1391 struct riva_par *par = info->par;
1402 if (par->riva.Architecture != NV_ARCH_03)
1405 color = par->palette[rect->color];
1418 riva_set_rop_solid(par, rop);
1420 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1421 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1423 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1424 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1427 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1430 riva_set_rop_solid(par, 0xcc);
1447 struct riva_par *par = info->par;
1454 RIVA_FIFO_FREE(par->riva, Blt, 3);
1455 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1457 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1460 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1493 struct riva_par *par = info->par;
1511 if (par->riva.Architecture != NV_ARCH_03) {
1515 fgx = par->palette[image->fg_color];
1516 bgx = par->palette[image->bg_color];
1523 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1524 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1526 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1529 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1530 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1531 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1533 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1535 NV_WR32(&par->riva.Bitmap->PointE, 0,
1538 d = &par->riva.Bitmap->MonochromeData01E;
1543 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1553 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1578 struct riva_par *par = info->par;
1586 par->riva.ShowHideCursor(&par->riva, 0);
1588 if (par->cursor_reset) {
1590 par->cursor_reset = 0;
1594 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1604 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1645 par->riva.LockUnlock(&par->riva, 0);
1647 rivafb_load_cursor_image(par, data, bg, fg,
1655 par->riva.ShowHideCursor(&par->riva, 1);
1662 struct riva_par *par = info->par;
1664 wait_for_idle(par);
1694 struct riva_par *par = info->par;
1705 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1714 info->pseudo_palette = par->pseudo_palette;
1730 struct riva_par *par = info->par;
1749 par->EDID = (unsigned char *)pedid;
1762 struct riva_par *par = info->par;
1767 par->riva.LockUnlock(&par->riva, 0);
1768 riva_create_i2c_busses(par);
1770 if (!par->chan[i].par)
1772 riva_probe_i2c_connector(par, i, &par->EDID);
1773 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1780 return (par->EDID) ? 1 : 0;
1837 struct riva_par *par = info->par;
1839 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1846 par->FlatPanel = 1;
1907 default_par = info->par;
2037 riva_bl_init(info->par);
2058 riva_delete_i2c_busses(info->par);
2080 struct riva_par *par = info->par;
2085 riva_delete_i2c_busses(par);
2086 kfree(par->EDID);
2092 arch_phys_wc_del(par->wc_cookie);
2093 iounmap(par->ctrl_base);
2095 if (par->riva.Architecture == NV_ARCH_03)
2096 iounmap(par->riva.PRAMIN);