Lines Matching refs:par
60 void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
62 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
63 VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
65 u8 NVReadCrtc(struct nvidia_par *par, u8 index)
67 VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
68 return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
70 void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
72 VGA_WR08(par->PVIO, VGA_GFX_I, index);
73 VGA_WR08(par->PVIO, VGA_GFX_D, value);
75 u8 NVReadGr(struct nvidia_par *par, u8 index)
77 VGA_WR08(par->PVIO, VGA_GFX_I, index);
78 return (VGA_RD08(par->PVIO, VGA_GFX_D));
80 void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
82 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
83 VGA_WR08(par->PVIO, VGA_SEQ_D, value);
85 u8 NVReadSeq(struct nvidia_par *par, u8 index)
87 VGA_WR08(par->PVIO, VGA_SEQ_I, index);
88 return (VGA_RD08(par->PVIO, VGA_SEQ_D));
90 void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
94 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
95 if (par->paletteEnabled)
99 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
100 VGA_WR08(par->PCIO, VGA_ATT_W, value);
102 u8 NVReadAttr(struct nvidia_par *par, u8 index)
106 tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
107 if (par->paletteEnabled)
111 VGA_WR08(par->PCIO, VGA_ATT_IW, index);
112 return (VGA_RD08(par->PCIO, VGA_ATT_R));
114 void NVWriteMiscOut(struct nvidia_par *par, u8 value)
116 VGA_WR08(par->PVIO, VGA_MIS_W, value);
118 u8 NVReadMiscOut(struct nvidia_par *par)
120 return (VGA_RD08(par->PVIO, VGA_MIS_R));
122 void NVWriteDacMask(struct nvidia_par *par, u8 value)
124 VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
126 void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
128 VGA_WR08(par->PDIO, VGA_PEL_IR, value);
130 void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
132 VGA_WR08(par->PDIO, VGA_PEL_IW, value);
134 void NVWriteDacData(struct nvidia_par *par, u8 value)
136 VGA_WR08(par->PDIO, VGA_PEL_D, value);
138 u8 NVReadDacData(struct nvidia_par *par)
140 return (VGA_RD08(par->PDIO, VGA_PEL_D));
143 static int NVIsConnected(struct nvidia_par *par, int output)
145 volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
163 NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
164 NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
177 NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608);
185 static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
188 par->PCIO = par->PCIO0 + 0x2000;
189 par->PCRTC = par->PCRTC0 + 0x800;
190 par->PRAMDAC = par->PRAMDAC0 + 0x800;
191 par->PDIO = par->PDIO0 + 0x2000;
193 par->PCIO = par->PCIO0;
194 par->PCRTC = par->PCRTC0;
195 par->PRAMDAC = par->PRAMDAC0;
196 par->PDIO = par->PDIO0;
200 static void nv4GetConfig(struct nvidia_par *par)
202 if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
203 par->RamAmountKBytes =
204 ((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
207 switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
209 par->RamAmountKBytes = 1024 * 32;
212 par->RamAmountKBytes = 1024 * 4;
215 par->RamAmountKBytes = 1024 * 8;
219 par->RamAmountKBytes = 1024 * 16;
223 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
225 par->CURSOR = &par->PRAMIN[0x1E00];
226 par->MinVClockFreqKHz = 12000;
227 par->MaxVClockFreqKHz = 350000;
230 static void nv10GetConfig(struct nvidia_par *par)
233 u32 implementation = par->Chipset & 0x0ff0;
237 if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
238 NV_WR32(par->PMC, 0x0004, 0x01000001);
243 dev = pci_get_domain_bus_and_slot(pci_domain_nr(par->pci_dev->bus),
245 if ((par->Chipset & 0xffff) == 0x01a0) {
249 par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
250 } else if ((par->Chipset & 0xffff) == 0x01f0) {
254 par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
256 par->RamAmountKBytes =
257 (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
261 par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
264 if (par->twoHeads && (implementation != 0x0110)) {
265 if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
266 par->CrystalFreqKHz = 27000;
269 par->CURSOR = NULL; /* can't set this here */
270 par->MinVClockFreqKHz = 12000;
271 par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
276 struct nvidia_par *par = info->par;
278 u16 implementation = par->Chipset & 0x0ff0;
298 par->PRAMIN = par->REGS + (0x00710000 / 4);
299 par->PCRTC0 = par->REGS + (0x00600000 / 4);
300 par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
301 par->PFB = par->REGS + (0x00100000 / 4);
302 par->PFIFO = par->REGS + (0x00002000 / 4);
303 par->PGRAPH = par->REGS + (0x00400000 / 4);
304 par->PEXTDEV = par->REGS + (0x00101000 / 4);
305 par->PTIMER = par->REGS + (0x00009000 / 4);
306 par->PMC = par->REGS + (0x00000000 / 4);
307 par->FIFO = par->REGS + (0x00800000 / 4);
310 par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
311 par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
312 par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
314 par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
319 par->fpScaler = (par->FpScale && par->twoHeads &&
322 par->twoStagePLL = (implementation == 0x0310) ||
323 (implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
325 par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
328 par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
331 switch (par->Chipset & 0xffff) {
386 if (par->Architecture == NV_ARCH_04)
387 nv4GetConfig(par);
389 nv10GetConfig(par);
391 NVSelectHeadRegisters(par, 0);
393 NVLockUnlock(par, 0);
395 par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
397 par->Television = 0;
399 nvidia_create_i2c_busses(par);
400 if (!par->twoHeads) {
401 par->CRTCnumber = 0;
411 if ((par->Chipset & 0x0fff) <= 0x0020)
414 VGA_WR08(par->PCIO, 0x03D4, 0x28);
415 if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
416 VGA_WR08(par->PCIO, 0x03D4, 0x33);
417 if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
428 if (par->FlatPanel == -1) {
429 par->FlatPanel = FlatPanel;
430 par->Television = Television;
433 "specified\n", par->FlatPanel ? "DFP" : "CRT");
444 if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
448 if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
452 analog_on_A = NVIsConnected(par, 0);
453 analog_on_B = NVIsConnected(par, 1);
461 VGA_WR08(par->PCIO, 0x03D4, 0x44);
462 cr44 = VGA_RD08(par->PCIO, 0x03D5);
464 VGA_WR08(par->PCIO, 0x03D5, 3);
465 NVSelectHeadRegisters(par, 1);
466 NVLockUnlock(par, 0);
468 VGA_WR08(par->PCIO, 0x03D4, 0x28);
469 slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
471 VGA_WR08(par->PCIO, 0x03D4, 0x33);
472 tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
475 VGA_WR08(par->PCIO, 0x03D4, 0x44);
476 VGA_WR08(par->PCIO, 0x03D5, 0);
477 NVSelectHeadRegisters(par, 0);
478 NVLockUnlock(par, 0);
480 VGA_WR08(par->PCIO, 0x03D4, 0x28);
481 slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
483 VGA_WR08(par->PCIO, 0x03D4, 0x33);
484 tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
487 oldhead = NV_RD32(par->PCRTC0, 0x00000860);
488 NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
544 if (par->FlatPanel == -1) {
546 par->FlatPanel = FlatPanel;
547 par->Television = Television;
554 par->FlatPanel = 1;
557 par->FlatPanel = 0;
562 "specified\n", par->FlatPanel ? "DFP" : "CRT");
565 if (par->CRTCnumber == -1) {
567 par->CRTCnumber = CRTCnumber;
571 if (par->FlatPanel)
572 par->CRTCnumber = 1;
574 par->CRTCnumber = 0;
576 par->CRTCnumber);
580 "specified\n", par->CRTCnumber);
585 par->FlatPanel) ||
587 !par->FlatPanel)) {
600 !par->FlatPanel) ||
602 par->FlatPanel)) {
610 cr44 = par->CRTCnumber * 0x3;
612 NV_WR32(par->PCRTC0, 0x00000860, oldhead);
614 VGA_WR08(par->PCIO, 0x03D4, 0x44);
615 VGA_WR08(par->PCIO, 0x03D5, cr44);
616 NVSelectHeadRegisters(par, par->CRTCnumber);
620 par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
621 par->CRTCnumber);
623 if (par->FlatPanel && !par->Television) {
624 par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
625 par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
626 par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
628 printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
634 if (!par->FlatPanel || !par->twoHeads)
635 par->FPDither = 0;
637 par->LVDS = 0;
638 if (par->FlatPanel && par->twoHeads) {
639 NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
640 if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1)
641 par->LVDS = 1;
642 printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");