Lines Matching refs:par
76 struct nvidia_par *par = info->par;
80 par->lockup = 1;
85 struct nvidia_par *par = info->par;
88 while (--count && READ_GET(par) != par->dmaPut) ;
98 struct nvidia_par *par = info->par;
101 while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;
109 static void NVDmaKickoff(struct nvidia_par *par)
111 if (par->dmaCurrent != par->dmaPut) {
112 par->dmaPut = par->dmaCurrent;
113 WRITE_PUT(par, par->dmaPut);
119 struct nvidia_par *par = info->par;
124 while (par->dmaFree < size && --count && !par->lockup) {
125 dmaGet = READ_GET(par);
127 if (par->dmaPut >= dmaGet) {
128 par->dmaFree = par->dmaMax - par->dmaCurrent;
129 if (par->dmaFree < size) {
130 NVDmaNext(par, 0x20000000);
132 if (par->dmaPut <= SKIPS)
133 WRITE_PUT(par, SKIPS + 1);
136 dmaGet = READ_GET(par);
140 par->lockup = 1;
143 WRITE_PUT(par, SKIPS);
144 par->dmaCurrent = par->dmaPut = SKIPS;
145 par->dmaFree = dmaGet - (SKIPS + 1);
148 par->dmaFree = dmaGet - par->dmaCurrent - 1;
160 struct nvidia_par *par = info->par;
162 NVDmaStart(info, par, PATTERN_COLOR_0, 4);
163 NVDmaNext(par, clr0);
164 NVDmaNext(par, clr1);
165 NVDmaNext(par, pat0);
166 NVDmaNext(par, pat1);
171 struct nvidia_par *par = info->par;
175 if (par->currentRop != (rop + 32)) {
176 NVDmaStart(info, par, ROP_SET, 1);
177 NVDmaNext(par, NVCopyROP_PM[rop]);
178 par->currentRop = rop + 32;
180 } else if (par->currentRop != rop) {
181 if (par->currentRop >= 16)
183 NVDmaStart(info, par, ROP_SET, 1);
184 NVDmaNext(par, NVCopyROP[rop]);
185 par->currentRop = rop;
192 struct nvidia_par *par = info->par;
196 NVDmaStart(info, par, CLIP_POINT, 2);
197 NVDmaNext(par, (y1 << 16) | x1);
198 NVDmaNext(par, (h << 16) | w);
203 struct nvidia_par *par = info->par;
209 par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);
212 NV_WR32(&par->dmaBase[i], 0, 0x00000000);
214 NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
215 NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
216 NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
217 NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
218 NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
219 NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
220 NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
221 NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
222 NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
223 NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
224 NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
225 NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
226 NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
227 NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
228 NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
229 NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);
231 par->dmaPut = 0;
232 par->dmaCurrent = 16 + SKIPS;
233 par->dmaMax = 8191;
234 par->dmaFree = par->dmaMax - par->dmaCurrent;
258 NVDmaStart(info, par, SURFACE_FORMAT, 4);
259 NVDmaNext(par, surfaceFormat);
260 NVDmaNext(par, pitch | (pitch << 16));
261 NVDmaNext(par, 0);
262 NVDmaNext(par, 0);
264 NVDmaStart(info, par, PATTERN_FORMAT, 1);
265 NVDmaNext(par, patternFormat);
267 NVDmaStart(info, par, RECT_FORMAT, 1);
268 NVDmaNext(par, rectFormat);
270 NVDmaStart(info, par, LINE_FORMAT, 1);
271 NVDmaNext(par, lineFormat);
273 par->currentRop = ~0; /* set to something invalid */
279 NVDmaKickoff(par);
284 struct nvidia_par *par = info->par;
289 if (!par->lockup)
292 if (!par->lockup)
300 struct nvidia_par *par = info->par;
305 if (par->lockup) {
310 NVDmaStart(info, par, BLIT_POINT_SRC, 3);
311 NVDmaNext(par, (region->sy << 16) | region->sx);
312 NVDmaNext(par, (region->dy << 16) | region->dx);
313 NVDmaNext(par, (region->height << 16) | region->width);
315 NVDmaKickoff(par);
320 struct nvidia_par *par = info->par;
326 if (par->lockup) {
339 NVDmaStart(info, par, RECT_SOLID_COLOR, 1);
340 NVDmaNext(par, color);
342 NVDmaStart(info, par, RECT_SOLID_RECTS(0), 2);
343 NVDmaNext(par, (rect->dx << 16) | rect->dy);
344 NVDmaNext(par, (rect->width << 16) | rect->height);
346 NVDmaKickoff(par);
355 struct nvidia_par *par = info->par;
371 NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
372 NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
373 NVDmaNext(par, ((image->dy + image->height) << 16) |
375 NVDmaNext(par, bg);
376 NVDmaNext(par, fg);
377 NVDmaNext(par, (image->height << 16) | width);
378 NVDmaNext(par, (image->height << 16) | width);
379 NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
382 NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0),
388 NVDmaNext(par, tmp);
395 NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);
400 NVDmaNext(par, tmp);
404 NVDmaKickoff(par);
409 struct nvidia_par *par = info->par;
414 if (image->depth == 1 && !par->lockup)