Lines Matching refs:mx3fb_write_reg
348 static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
370 mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
381 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
482 mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
529 mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
537 mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
548 mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
549 mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
550 mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
553 mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
590 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
597 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
605 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
608 mx3fb_write_reg(mx3fb, map->b0, DI_DISP3_B0_MAP);
609 mx3fb_write_reg(mx3fb, map->b1, DI_DISP3_B1_MAP);
610 mx3fb_write_reg(mx3fb, map->b2, DI_DISP3_B2_MAP);
648 mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
655 mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
679 mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
682 mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
685 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
707 mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
1483 mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);