Lines Matching refs:m1
666 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
672 m = (5 * (m1 + 2)) + (m2 + 2);
716 int i, m1, m2, n, p1, p2;
728 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
733 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
734 m1, m2, n, p1, p2);
736 calc_vclock(index, m1, m2, n, p1, p2, 0));
739 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
743 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
744 m1, m2, n, p1, p2);
746 calc_vclock(index, m1, m2, n, p1, p2, 0));
756 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
761 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
762 m1, m2, n, p1, p2);
764 calc_vclock(index, m1, m2, n, p1, p2, 0));
767 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
772 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
773 m1, m2, n, p1, p2);
775 calc_vclock(index, m1, m2, n, p1, p2, 0));
883 int m1, m2;
888 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
890 testm = (5 * (m1 + 2)) + (m2 + 2);
892 *retm1 = (unsigned int)m1;
940 u32 m1, m2, n, p1, p2, n1, testm;
979 if (splitm(index, testm, &m1, &m2)) {
1008 splitm(index, m, &m1, &m2);
1014 m, m1, m2, n, n1, p, p1, p2,
1016 calc_vclock(index, m1, m2, n1, p1, p2, 0),
1018 *retm1 = m1;
1023 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
1046 u32 m1, m2, n, p1, p2, clock_target, clock;
1115 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1126 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1144 (m1 << FP_M1_DIVISOR_SHIFT) |