Lines Matching refs:dinfo
67 int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
70 if (!pdev || !dinfo)
75 dinfo->name = "Intel(R) 830M";
76 dinfo->chipset = INTEL_830M;
77 dinfo->mobile = 1;
78 dinfo->pll_index = PLLS_I8xx;
81 dinfo->name = "Intel(R) 845G";
82 dinfo->chipset = INTEL_845G;
83 dinfo->mobile = 0;
84 dinfo->pll_index = PLLS_I8xx;
87 dinfo->mobile = 1;
88 dinfo->name = "Intel(R) 854";
89 dinfo->chipset = INTEL_854;
93 dinfo->mobile = 1;
94 dinfo->pll_index = PLLS_I8xx;
99 dinfo->name = "Intel(R) 855GME";
100 dinfo->chipset = INTEL_855GME;
103 dinfo->name = "Intel(R) 855GM";
104 dinfo->chipset = INTEL_855GM;
107 dinfo->name = "Intel(R) 852GME";
108 dinfo->chipset = INTEL_852GME;
111 dinfo->name = "Intel(R) 852GM";
112 dinfo->chipset = INTEL_852GM;
115 dinfo->name = "Intel(R) 852GM/855GM";
116 dinfo->chipset = INTEL_85XGM;
121 dinfo->name = "Intel(R) 865G";
122 dinfo->chipset = INTEL_865G;
123 dinfo->mobile = 0;
124 dinfo->pll_index = PLLS_I8xx;
127 dinfo->name = "Intel(R) 915G";
128 dinfo->chipset = INTEL_915G;
129 dinfo->mobile = 0;
130 dinfo->pll_index = PLLS_I9xx;
133 dinfo->name = "Intel(R) 915GM";
134 dinfo->chipset = INTEL_915GM;
135 dinfo->mobile = 1;
136 dinfo->pll_index = PLLS_I9xx;
139 dinfo->name = "Intel(R) 945G";
140 dinfo->chipset = INTEL_945G;
141 dinfo->mobile = 0;
142 dinfo->pll_index = PLLS_I9xx;
145 dinfo->name = "Intel(R) 945GM";
146 dinfo->chipset = INTEL_945GM;
147 dinfo->mobile = 1;
148 dinfo->pll_index = PLLS_I9xx;
151 dinfo->name = "Intel(R) 945GME";
152 dinfo->chipset = INTEL_945GME;
153 dinfo->mobile = 1;
154 dinfo->pll_index = PLLS_I9xx;
157 dinfo->name = "Intel(R) 965G";
158 dinfo->chipset = INTEL_965G;
159 dinfo->mobile = 0;
160 dinfo->pll_index = PLLS_I9xx;
163 dinfo->name = "Intel(R) 965GM";
164 dinfo->chipset = INTEL_965GM;
165 dinfo->mobile = 1;
166 dinfo->pll_index = PLLS_I9xx;
282 int intelfbhw_check_non_crt(struct intelfb_info *dinfo)
313 int intelfbhw_validate_mode(struct intelfb_info *dinfo,
329 if (tmp > dinfo->fb.size) {
332 BtoKB(tmp), BtoKB(dinfo->fb.size));
385 struct intelfb_info *dinfo = GET_DINFO(info);
399 offset = (yoffset * dinfo->pitch) +
402 offset += dinfo->fb.offset << 12;
404 dinfo->vsync.pan_offset = offset;
406 !intelfbhw_enable_irq(dinfo))
407 dinfo->vsync.pan_display = 1;
409 dinfo->vsync.pan_display = 0;
419 struct intelfb_info *dinfo = GET_DINFO(info);
439 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
441 if (dinfo->cursor_on) {
443 intelfbhw_cursor_hide(dinfo);
445 intelfbhw_cursor_show(dinfo);
446 dinfo->cursor_on = 1;
448 dinfo->cursor_blanked = blank;
499 void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
503 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
518 int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
527 if (!hw || !dinfo)
684 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
689 if (IS_I9XX(dinfo)) {
712 void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
717 int index = dinfo->pll_index;
731 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
742 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
759 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
770 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
1040 int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
1115 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1137 if (IS_I9XX(dinfo)) {
1248 hw->disp_a_stride = dinfo->pitch;
1254 hw->disp_a_base += dinfo->fb.offset << 12;
1257 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1277 int intelfbhw_program_mode(struct intelfb_info *dinfo,
1300 dinfo->pipe = intelfbhw_active_pipe(hw);
1302 if (dinfo->pipe == PIPE_B) {
1429 switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED |
1450 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1482 static void refresh_ring(struct intelfb_info *dinfo);
1483 static void reset_state(struct intelfb_info *dinfo);
1484 static void do_flush(struct intelfb_info *dinfo);
1486 static u32 get_ring_space(struct intelfb_info *dinfo)
1490 if (dinfo->ring_tail >= dinfo->ring_head)
1491 ring_space = dinfo->ring.size -
1492 (dinfo->ring_tail - dinfo->ring_head);
1494 ring_space = dinfo->ring_head - dinfo->ring_tail;
1504 static int wait_ring(struct intelfb_info *dinfo, int n)
1515 while (dinfo->ring_space < n) {
1516 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1517 dinfo->ring_space = get_ring_space(dinfo);
1519 if (dinfo->ring_head != last_head) {
1521 last_head = dinfo->ring_head;
1527 reset_state(dinfo);
1528 refresh_ring(dinfo);
1529 do_flush(dinfo);
1534 dinfo->ring_space, n);
1537 dinfo->ring_lockup = 1;
1546 static void do_flush(struct intelfb_info *dinfo)
1554 void intelfbhw_do_sync(struct intelfb_info *dinfo)
1560 if (!dinfo->accel)
1568 do_flush(dinfo);
1569 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1570 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1573 static void refresh_ring(struct intelfb_info *dinfo)
1579 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1580 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1581 dinfo->ring_space = get_ring_space(dinfo);
1584 static void reset_state(struct intelfb_info *dinfo)
1602 refresh_ring(dinfo);
1603 intelfbhw_do_sync(dinfo);
1614 void intelfbhw_2d_stop(struct intelfb_info *dinfo)
1618 dinfo->accel, dinfo->ring_active);
1621 if (!dinfo->accel)
1624 dinfo->ring_active = 0;
1625 reset_state(dinfo);
1633 void intelfbhw_2d_start(struct intelfb_info *dinfo)
1637 dinfo->accel, dinfo->ring_active);
1640 if (!dinfo->accel)
1648 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1650 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1652 refresh_ring(dinfo);
1653 dinfo->ring_active = 1;
1657 void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w,
1668 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1696 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1697 dinfo->ring_tail, dinfo->ring_space);
1702 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1713 br09 = dinfo->fb_start;
1715 br12 = dinfo->fb_start;
1747 int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1784 br09 = dinfo->fb_start;
1836 void intelfbhw_cursor_init(struct intelfb_info *dinfo)
1844 if (dinfo->mobile || IS_I9XX(dinfo)) {
1845 if (!dinfo->cursor.physical)
1853 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1860 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1867 void intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1875 dinfo->cursor_on = 0;
1876 if (dinfo->mobile || IS_I9XX(dinfo)) {
1877 if (!dinfo->cursor.physical)
1884 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1892 void intelfbhw_cursor_show(struct intelfb_info *dinfo)
1900 dinfo->cursor_on = 1;
1902 if (dinfo->cursor_blanked)
1905 if (dinfo->mobile || IS_I9XX(dinfo)) {
1906 if (!dinfo->cursor.physical)
1913 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1921 void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1939 if (IS_I9XX(dinfo))
1940 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1943 void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1955 void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1958 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1966 if (!dinfo->cursor.virtual)
1984 void intelfbhw_cursor_reset(struct intelfb_info *dinfo)
1986 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1993 if (!dinfo->cursor.virtual)
2008 struct intelfb_info *dinfo = dev_id;
2010 spin_lock(&dinfo->int_lock);
2013 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2019 spin_unlock(&dinfo->int_lock);
2027 if (dinfo->vsync.pan_display) {
2028 dinfo->vsync.pan_display = 0;
2029 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2032 dinfo->vsync.count++;
2033 wake_up_interruptible(&dinfo->vsync.wait);
2035 spin_unlock(&dinfo->int_lock);
2040 int intelfbhw_enable_irq(struct intelfb_info *dinfo)
2043 if (!test_and_set_bit(0, &dinfo->irq_flags)) {
2044 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
2045 "intelfb", dinfo)) {
2046 clear_bit(0, &dinfo->irq_flags);
2050 spin_lock_irq(&dinfo->int_lock);
2054 spin_lock_irq(&dinfo->int_lock);
2056 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED)
2065 spin_unlock_irq(&dinfo->int_lock);
2069 void intelfbhw_disable_irq(struct intelfb_info *dinfo)
2071 if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2072 if (dinfo->vsync.pan_display) {
2073 dinfo->vsync.pan_display = 0;
2074 OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2076 spin_lock_irq(&dinfo->int_lock);
2082 spin_unlock_irq(&dinfo->int_lock);
2084 free_irq(dinfo->pdev->irq, dinfo);
2088 int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
2096 vsync = &dinfo->vsync;
2102 ret = intelfbhw_enable_irq(dinfo);