Lines Matching defs:tmp
69 u32 tmp;
92 tmp = 0;
95 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
96 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
177 u16 tmp;
192 tmp = 0;
193 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
213 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
226 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
244 tmp & INTEL_830_GMCH_GMS_MASK);
249 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
276 tmp & INTEL_855_GMCH_GMS_MASK);
317 int tmp;
328 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
329 if (tmp > dinfo->fb.size) {
332 BtoKB(tmp), BtoKB(dinfo->fb.size));
368 tmp = 1000000000 / var->pixclock;
369 if (tmp < MIN_CLOCK) {
371 (tmp + 500) / 1000, MIN_CLOCK / 1000);
374 if (tmp > MAX_CLOCK) {
376 (tmp + 500) / 1000, MAX_CLOCK / 1000);
420 u32 tmp;
427 tmp = INREG(DSPACNTR);
429 tmp &= ~DISPPLANE_PLANE_ENABLE;
431 tmp |= DISPPLANE_PLANE_ENABLE;
432 OUTREG(DSPACNTR, tmp);
434 tmp = INREG(DSPABASE);
435 OUTREG(DSPABASE, tmp);
451 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
455 tmp |= ADPA_DPMS_D0;
458 tmp |= ADPA_DPMS_D1;
461 tmp |= ADPA_DPMS_D2;
464 tmp |= ADPA_DPMS_D3;
467 OUTREG(ADPA, tmp);
1280 u32 tmp;
1296 tmp = INREG(VGACNTRL);
1297 tmp |= VGA_DISABLE;
1298 OUTREG(VGACNTRL, tmp);
1353 tmp = INREG(pipe_conf_reg);
1354 tmp &= ~PIPECONF_ENABLE;
1355 OUTREG(pipe_conf_reg, tmp);
1365 tmp = INREG(pipe_conf_reg);
1366 tmp &= ~PIPECONF_ENABLE;
1367 OUTREG(pipe_conf_reg, tmp);
1374 tmp = INREG(DSPACNTR);
1375 tmp &= ~DISPPLANE_PLANE_ENABLE;
1376 OUTREG(DSPACNTR, tmp);
1377 tmp = INREG(DSPBCNTR);
1378 tmp &= ~DISPPLANE_PLANE_ENABLE;
1379 OUTREG(DSPBCNTR, tmp);
1389 tmp = INREG(ADPA);
1390 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1391 tmp |= ADPA_DPMS_D3;
1392 OUTREG(ADPA, tmp);
1398 tmp = INREG(dpll_reg);
1399 tmp &= ~DPLL_VCO_ENABLE;
1400 OUTREG(dpll_reg, tmp);
1444 tmp = INREG(ADPA);
1445 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1446 tmp |= ADPA_DPMS_D0;
1447 OUTREG(ADPA, tmp);
1456 tmp = INREG(DSPACNTR);
1457 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1458 tmp |= DISPPLANE_PLANE_ENABLE;
1459 OUTREG(DSPACNTR, tmp);
1472 tmp = INREG(DSPACNTR);
1473 tmp |= DISPPLANE_PLANE_ENABLE;
1474 OUTREG(DSPACNTR, tmp);
1587 u32 tmp;
1597 tmp = INREG(PRI_RING_LENGTH);
1598 if (tmp & RING_ENABLE) {
1751 int nbytes, ndwords, pad, tmp;
1782 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1783 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1838 u32 tmp;
1847 tmp = INREG(CURSOR_A_CONTROL);
1848 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1851 tmp |= CURSOR_MODE_DISABLE;
1852 OUTREG(CURSOR_A_CONTROL, tmp);
1855 tmp = INREG(CURSOR_CONTROL);
1856 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1858 tmp |= CURSOR_FORMAT_3C;
1859 OUTREG(CURSOR_CONTROL, tmp);
1861 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1863 OUTREG(CURSOR_SIZE, tmp);
1869 u32 tmp;
1879 tmp = INREG(CURSOR_A_CONTROL);
1880 tmp &= ~CURSOR_MODE_MASK;
1881 tmp |= CURSOR_MODE_DISABLE;
1882 OUTREG(CURSOR_A_CONTROL, tmp);
1886 tmp = INREG(CURSOR_CONTROL);
1887 tmp &= ~CURSOR_ENABLE;
1888 OUTREG(CURSOR_CONTROL, tmp);
1894 u32 tmp;
1908 tmp = INREG(CURSOR_A_CONTROL);
1909 tmp &= ~CURSOR_MODE_MASK;
1910 tmp |= CURSOR_MODE_64_4C_AX;
1911 OUTREG(CURSOR_A_CONTROL, tmp);
1915 tmp = INREG(CURSOR_CONTROL);
1916 tmp |= CURSOR_ENABLE;
1917 OUTREG(CURSOR_CONTROL, tmp);
1923 u32 tmp;
1935 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1937 OUTREG(CURSOR_A_POSITION, tmp);
2007 u16 tmp;
2012 tmp = INREG16(IIR);
2014 tmp &= PIPE_A_EVENT_INTERRUPT;
2016 tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
2018 if (tmp == 0) {
2026 OUTREG16(IIR, tmp);
2042 u16 tmp;
2057 tmp = PIPE_A_EVENT_INTERRUPT;
2059 tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */
2060 if (tmp != INREG16(IER)) {
2061 DBG_MSG("changing IER to 0x%X\n", tmp);
2062 OUTREG16(IER, tmp);