Lines Matching defs:par
423 getclkMHz(struct imstt_par *par)
427 clk_m = par->init.pclk_m;
428 clk_n = par->init.pclk_n;
429 clk_p = par->init.pclk_p;
435 setclkMHz(struct imstt_par *par, __u32 MHz)
461 par->init.pclk_m = clk_m;
462 par->init.pclk_n = clk_n;
463 par->init.pclk_p = 0;
467 compute_imstt_regvals_ibm(struct imstt_par *par, int xres, int yres)
469 struct imstt_regvals *init = &par->init;
501 setclkMHz(par, MHz);
518 compute_imstt_regvals_tvp(struct imstt_par *par, int xres, int yres)
547 par->init = *init;
552 compute_imstt_regvals (struct imstt_par *par, u_int xres, u_int yres)
554 if (par->ramdac == IBM)
555 return compute_imstt_regvals_ibm(par, xres, yres);
557 return compute_imstt_regvals_tvp(par, xres, yres);
561 set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp)
563 struct imstt_regvals *init = &par->init;
566 par->cmap_regs[PIDXHI] = 0; eieio();
567 par->cmap_regs[PIDXLO] = PIXM0; eieio();
568 par->cmap_regs[PIDXDATA] = init->pclk_m;eieio();
569 par->cmap_regs[PIDXLO] = PIXN0; eieio();
570 par->cmap_regs[PIDXDATA] = init->pclk_n;eieio();
571 par->cmap_regs[PIDXLO] = PIXP0; eieio();
572 par->cmap_regs[PIDXDATA] = init->pclk_p;eieio();
573 par->cmap_regs[PIDXLO] = PIXC0; eieio();
574 par->cmap_regs[PIDXDATA] = 0x02; eieio();
576 par->cmap_regs[PIDXLO] = PIXFMT; eieio();
577 par->cmap_regs[PIDXDATA] = pformat; eieio();
581 set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp)
583 struct imstt_regvals *init = &par->init;
620 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
621 par->cmap_regs[TVPIDATA] = 0x00; eieio();
622 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
623 par->cmap_regs[TVPIDATA] = init->pclk_m; eieio();
624 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
625 par->cmap_regs[TVPIDATA] = init->pclk_n; eieio();
626 par->cmap_regs[TVPADDRW] = TVPIRPPD; eieio();
627 par->cmap_regs[TVPIDATA] = init->pclk_p; eieio();
629 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
630 par->cmap_regs[TVPIDATA] = tcc; eieio();
631 par->cmap_regs[TVPADDRW] = TVPIRMXC; eieio();
632 par->cmap_regs[TVPIDATA] = mxc; eieio();
633 par->cmap_regs[TVPADDRW] = TVPIRMIC; eieio();
634 par->cmap_regs[TVPIDATA] = mic; eieio();
636 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
637 par->cmap_regs[TVPIDATA] = 0x00; eieio();
638 par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
639 par->cmap_regs[TVPIDATA] = lckl_n; eieio();
641 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
642 par->cmap_regs[TVPIDATA] = 0x15; eieio();
643 par->cmap_regs[TVPADDRW] = TVPIRMLC; eieio();
644 par->cmap_regs[TVPIDATA] = mlc; eieio();
646 par->cmap_regs[TVPADDRW] = TVPIRPLA; eieio();
647 par->cmap_regs[TVPIDATA] = 0x2a; eieio();
648 par->cmap_regs[TVPADDRW] = TVPIRLPD; eieio();
649 par->cmap_regs[TVPIDATA] = lckl_p; eieio();
655 struct imstt_par *par = info->par;
656 struct imstt_regvals *init = &par->init;
659 if (par->ramdac == IBM)
660 set_imstt_regvals_ibm(par, bpp);
662 set_imstt_regvals_tvp(par, bpp);
698 if (par->ramdac == TVP)
701 write_reg_le32(par->dc_regs, HES, init->hes);
702 write_reg_le32(par->dc_regs, HEB, init->heb);
703 write_reg_le32(par->dc_regs, HSB, init->hsb);
704 write_reg_le32(par->dc_regs, HT, init->ht);
705 write_reg_le32(par->dc_regs, VES, init->ves);
706 write_reg_le32(par->dc_regs, VEB, init->veb);
707 write_reg_le32(par->dc_regs, VSB, init->vsb);
708 write_reg_le32(par->dc_regs, VT, init->vt);
709 write_reg_le32(par->dc_regs, VIL, init->vil);
710 write_reg_le32(par->dc_regs, HCIV, 1);
711 write_reg_le32(par->dc_regs, VCIV, 1);
712 write_reg_le32(par->dc_regs, TCDR, 4);
713 write_reg_le32(par->dc_regs, RRCIV, 1);
714 write_reg_le32(par->dc_regs, RRSC, 0x980);
715 write_reg_le32(par->dc_regs, RRCR, 0x11);
717 if (par->ramdac == IBM) {
718 write_reg_le32(par->dc_regs, HRIR, 0x0100);
719 write_reg_le32(par->dc_regs, CMR, 0x00ff);
720 write_reg_le32(par->dc_regs, SRGCTL, 0x0073);
722 write_reg_le32(par->dc_regs, HRIR, 0x0200);
723 write_reg_le32(par->dc_regs, CMR, 0x01ff);
724 write_reg_le32(par->dc_regs, SRGCTL, 0x0003);
739 write_reg_le32(par->dc_regs, SCR, scr);
740 write_reg_le32(par->dc_regs, SPR, pitch);
741 write_reg_le32(par->dc_regs, STGCTL, ctl);
747 struct imstt_par *par = info->par;
750 write_reg_le32(par->dc_regs, SSR, off);
754 set_555 (struct imstt_par *par)
756 if (par->ramdac == IBM) {
757 par->cmap_regs[PIDXHI] = 0; eieio();
758 par->cmap_regs[PIDXLO] = BPP16; eieio();
759 par->cmap_regs[PIDXDATA] = 0x01; eieio();
761 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
762 par->cmap_regs[TVPIDATA] = 0x44; eieio();
767 set_565 (struct imstt_par *par)
769 if (par->ramdac == IBM) {
770 par->cmap_regs[PIDXHI] = 0; eieio();
771 par->cmap_regs[PIDXLO] = BPP16; eieio();
772 par->cmap_regs[PIDXDATA] = 0x03; eieio();
774 par->cmap_regs[TVPADDRW] = TVPIRTCC; eieio();
775 par->cmap_regs[TVPIDATA] = 0x45; eieio();
861 struct imstt_par *par = info->par;
863 if (!compute_imstt_regvals(par, info->var.xres, info->var.yres))
867 set_565(par);
869 set_555(par);
871 info->var.pixclock = 1000000 / getclkMHz(par);
879 struct imstt_par *par = info->par;
891 par->cmap_regs[PADDRW] = regno << 3;
893 par->cmap_regs[PADDRW] = regno;
896 par->cmap_regs[PDATA] = red; eieio();
897 par->cmap_regs[PDATA] = green; eieio();
898 par->cmap_regs[PDATA] = blue; eieio();
903 par->palette[regno] =
908 par->palette[regno] =
913 par->palette[regno] = (i << 16) |i;
936 struct imstt_par *par = info->par;
939 ctrl = read_reg_le32(par->dc_regs, STGCTL);
945 if (par->ramdac == IBM) {
946 par->cmap_regs[PIDXHI] = 0; eieio();
947 par->cmap_regs[PIDXLO] = MISCTL2; eieio();
948 par->cmap_regs[PIDXDATA] = 0x55; eieio();
949 par->cmap_regs[PIDXLO] = MISCTL1; eieio();
950 par->cmap_regs[PIDXDATA] = 0x11; eieio();
951 par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
952 par->cmap_regs[PIDXDATA] = 0x0f; eieio();
953 par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
954 par->cmap_regs[PIDXDATA] = 0x1f; eieio();
955 par->cmap_regs[PIDXLO] = CLKCTL; eieio();
956 par->cmap_regs[PIDXDATA] = 0xc0;
967 if (par->ramdac == IBM) {
969 par->cmap_regs[PIDXHI] = 0; eieio();
970 par->cmap_regs[PIDXLO] = CLKCTL; eieio();
971 par->cmap_regs[PIDXDATA] = 0x01; eieio();
972 par->cmap_regs[PIDXLO] = PWRMNGMT; eieio();
973 par->cmap_regs[PIDXDATA] = 0x00; eieio();
974 par->cmap_regs[PIDXLO] = SYNCCTL; eieio();
975 par->cmap_regs[PIDXDATA] = 0x00; eieio();
976 par->cmap_regs[PIDXLO] = MISCTL1; eieio();
977 par->cmap_regs[PIDXDATA] = 0x01; eieio();
978 par->cmap_regs[PIDXLO] = MISCTL2; eieio();
979 par->cmap_regs[PIDXDATA] = 0x45; eieio();
983 write_reg_le32(par->dc_regs, STGCTL, ctrl);
990 struct imstt_par *par = info->par;
1008 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1009 write_reg_le32(par->dc_regs, DSA, dy + dx);
1010 write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
1011 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
1012 write_reg_le32(par->dc_regs, BI, 0xffffffff);
1013 write_reg_le32(par->dc_regs, MBC, 0xffffffff);
1014 write_reg_le32(par->dc_regs, CLR, bgc);
1015 write_reg_le32(par->dc_regs, BLTCTL, 0x840); /* 0x200000 */
1016 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1017 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1019 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1020 write_reg_le32(par->dc_regs, DSA, dy + dx);
1021 write_reg_le32(par->dc_regs, S1SA, dy + dx);
1022 write_reg_le32(par->dc_regs, CNT, (height << 16) | width);
1023 write_reg_le32(par->dc_regs, DP_OCTL, line_pitch);
1024 write_reg_le32(par->dc_regs, SP, line_pitch);
1025 write_reg_le32(par->dc_regs, BLTCTL, 0x40005);
1026 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1027 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1034 struct imstt_par *par = info->par;
1074 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1075 write_reg_le32(par->dc_regs, S1SA, fb_offset_old);
1076 write_reg_le32(par->dc_regs, SP, sp);
1077 write_reg_le32(par->dc_regs, DSA, fb_offset_new);
1078 write_reg_le32(par->dc_regs, CNT, cnt);
1079 write_reg_le32(par->dc_regs, DP_OCTL, dp_octl);
1080 write_reg_le32(par->dc_regs, BLTCTL, bltctl);
1081 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x80);
1082 while(read_reg_le32(par->dc_regs, SSTATUS) & 0x40);
1087 imsttfb_load_cursor_image(struct imstt_par *par, int width, int height, __u8 fgc)
1094 if (par->ramdac == IBM) {
1095 par->cmap_regs[PIDXHI] = 1; eieio();
1097 par->cmap_regs[PIDXLO] = x; eieio();
1098 par->cmap_regs[PIDXDATA] = 0x00; eieio();
1100 par->cmap_regs[PIDXHI] = 1; eieio();
1103 par->cmap_regs[PIDXLO] = x + y * 8; eieio();
1104 par->cmap_regs[PIDXDATA] = 0xff; eieio();
1106 par->cmap_regs[PIDXHI] = 0; eieio();
1107 par->cmap_regs[PIDXLO] = CURS1R; eieio();
1108 par->cmap_regs[PIDXDATA] = fgc; eieio();
1109 par->cmap_regs[PIDXLO] = CURS1G; eieio();
1110 par->cmap_regs[PIDXDATA] = fgc; eieio();
1111 par->cmap_regs[PIDXLO] = CURS1B; eieio();
1112 par->cmap_regs[PIDXDATA] = fgc; eieio();
1113 par->cmap_regs[PIDXLO] = CURS2R; eieio();
1114 par->cmap_regs[PIDXDATA] = fgc; eieio();
1115 par->cmap_regs[PIDXLO] = CURS2G; eieio();
1116 par->cmap_regs[PIDXDATA] = fgc; eieio();
1117 par->cmap_regs[PIDXLO] = CURS2B; eieio();
1118 par->cmap_regs[PIDXDATA] = fgc; eieio();
1119 par->cmap_regs[PIDXLO] = CURS3R; eieio();
1120 par->cmap_regs[PIDXDATA] = fgc; eieio();
1121 par->cmap_regs[PIDXLO] = CURS3G; eieio();
1122 par->cmap_regs[PIDXDATA] = fgc; eieio();
1123 par->cmap_regs[PIDXLO] = CURS3B; eieio();
1124 par->cmap_regs[PIDXDATA] = fgc; eieio();
1126 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1127 par->cmap_regs[TVPIDATA] &= 0x03; eieio();
1128 par->cmap_regs[TVPADDRW] = 0; eieio();
1130 par->cmap_regs[TVPCRDAT] = 0x00; eieio();
1133 par->cmap_regs[TVPCRDAT] = 0xff; eieio();
1135 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1136 par->cmap_regs[TVPIDATA] &= 0x03; eieio();
1139 par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
1140 par->cmap_regs[TVPCRDAT] = 0xff; eieio();
1142 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1143 par->cmap_regs[TVPIDATA] |= 0x08; eieio();
1146 par->cmap_regs[TVPADDRW] = x + y * 8; eieio();
1147 par->cmap_regs[TVPCRDAT] = 0xff; eieio();
1149 par->cmap_regs[TVPCADRW] = 0x00; eieio();
1151 par->cmap_regs[TVPCDATA] = fgc;
1159 imstt_set_cursor(struct imstt_par *par, struct fb_image *d, int on)
1161 if (par->ramdac == IBM) {
1162 par->cmap_regs[PIDXHI] = 0; eieio();
1164 par->cmap_regs[PIDXLO] = CURSCTL; eieio();
1165 par->cmap_regs[PIDXDATA] = 0x00; eieio();
1167 par->cmap_regs[PIDXLO] = CURSXHI; eieio();
1168 par->cmap_regs[PIDXDATA] = d->dx >> 8; eieio();
1169 par->cmap_regs[PIDXLO] = CURSXLO; eieio();
1170 par->cmap_regs[PIDXDATA] = d->dx & 0xff;eieio();
1171 par->cmap_regs[PIDXLO] = CURSYHI; eieio();
1172 par->cmap_regs[PIDXDATA] = d->dy >> 8; eieio();
1173 par->cmap_regs[PIDXLO] = CURSYLO; eieio();
1174 par->cmap_regs[PIDXDATA] = d->dy & 0xff;eieio();
1175 par->cmap_regs[PIDXLO] = CURSCTL; eieio();
1176 par->cmap_regs[PIDXDATA] = 0x02; eieio();
1180 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1181 par->cmap_regs[TVPIDATA] = 0x00; eieio();
1185 par->cmap_regs[TVPCXPOH] = x >> 8; eieio();
1186 par->cmap_regs[TVPCXPOL] = x & 0xff; eieio();
1187 par->cmap_regs[TVPCYPOH] = y >> 8; eieio();
1188 par->cmap_regs[TVPCYPOL] = y & 0xff; eieio();
1189 par->cmap_regs[TVPADDRW] = TVPIRICC; eieio();
1190 par->cmap_regs[TVPIDATA] = 0x02; eieio();
1198 struct imstt_par *par = info->par;
1250 imsttfb_load_cursor_image(par, xx, yy, fgc);
1268 struct imstt_par *par = info->par;
1277 write_reg_le32(par->dc_regs, reg[0], reg[1]);
1282 reg[1] = read_reg_le32(par->dc_regs, reg[0]);
1289 write_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0], reg[1]);
1294 reg[1] = read_reg_le32(((u_int __iomem *)par->cmap_regs), reg[0]);
1301 par->cmap_regs[PIDXHI] = 0; eieio();
1302 par->cmap_regs[PIDXLO] = idx[0]; eieio();
1303 par->cmap_regs[PIDXDATA] = idx[1]; eieio();
1308 par->cmap_regs[PIDXHI] = 0; eieio();
1309 par->cmap_regs[PIDXLO] = idx[0]; eieio();
1310 idx[1] = par->cmap_regs[PIDXDATA];
1351 struct imstt_par *par = info->par;
1354 tmp = read_reg_le32(par->dc_regs, PRC);
1355 if (par->ramdac == IBM)
1366 tmp = read_reg_le32(par->dc_regs, STGCTL);
1367 write_reg_le32(par->dc_regs, STGCTL, tmp & ~0x1);
1368 write_reg_le32(par->dc_regs, SSR, 0);
1371 if (par->ramdac == IBM) {
1372 par->cmap_regs[PPMASK] = 0xff;
1374 par->cmap_regs[PIDXHI] = 0;
1377 par->cmap_regs[PIDXLO] = ibm_initregs[i].addr;
1379 par->cmap_regs[PIDXDATA] = ibm_initregs[i].value;
1384 par->cmap_regs[TVPADDRW] = tvp_initregs[i].addr;
1386 par->cmap_regs[TVPIDATA] = tvp_initregs[i].value;
1419 || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) {
1425 sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP");
1438 // if (par->ramdac == IBM)
1441 set_565(par);
1443 set_555(par);
1446 info->var.pixclock = 1000000 / getclkMHz(par);
1461 tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8;
1470 struct imstt_par *par;
1485 par = info->par;
1498 par->ramdac = IBM;
1501 par->ramdac = TVP;
1504 par->ramdac = TVP;
1514 info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ?
1519 par->dc_regs = ioremap(addr + 0x800000, 0x1000);
1520 if (!par->dc_regs)
1522 par->cmap_regs_phys = addr + 0x840000;
1523 par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000);
1524 if (!par->cmap_regs)
1526 info->pseudo_palette = par->palette;
1535 iounmap(par->cmap_regs);
1537 iounmap(par->dc_regs);
1550 struct imstt_par *par = info->par;
1554 iounmap(par->cmap_regs);
1555 iounmap(par->dc_regs);