Lines Matching refs:XRX
128 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
129 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
136 i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
137 i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
144 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
146 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
153 i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
155 return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
755 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
759 i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
760 i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
761 i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
762 i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
764 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
820 i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
821 i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
822 i740outreg_mask(par, XRX, DISPLAY_CNTL,
824 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
825 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
827 i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
829 i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
837 i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
840 i740outreg_mask(par, XRX, IO_CTNL,
986 i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
1055 if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
1057 i740outb(par, XRX, DRAM_ROW_BNDRY_1);
1059 i740outb(par, XRX, DRAM_ROW_BNDRY_0);
1060 info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
1062 tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);