Lines Matching defs:par

299 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
314 start = par->dma_start;
315 end = par->dma_end;
334 start = par->p_palette_base;
335 end = start + par->palette_sz - 1;
511 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
563 par->palette_sz = 16 * 2;
579 par->palette_sz = 256 * 2;
596 struct da8xx_fb_par *par = info->par;
597 unsigned short *palette = (unsigned short *) par->v_palette_base;
676 lcd_blit(LOAD_PALETTE, par);
696 static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par,
702 if (par->lcdc_clk_rate != lcdc_clk_rate) {
703 ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate);
705 dev_err(par->dev,
710 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
724 static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
732 *lcdc_clk_rate = par->lcdc_clk_rate;
735 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
739 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
749 static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
753 unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock,
756 return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate);
759 static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
764 lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate);
768 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
774 ret = da8xx_fb_calc_config_clk_divider(par, panel);
776 dev_err(par->dev, "unable to configure clock\n");
807 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
823 struct da8xx_fb_par *par = arg;
845 lcd_blit(LOAD_DATA, par);
850 par->which_dma_channel_done = 0;
851 lcdc_write(par->dma_start,
853 lcdc_write(par->dma_end,
855 par->vsync_flag = 1;
856 wake_up_interruptible(&par->vsync_wait);
860 par->which_dma_channel_done = 1;
861 lcdc_write(par->dma_start,
863 lcdc_write(par->dma_end,
865 par->vsync_flag = 1;
866 wake_up_interruptible(&par->vsync_wait);
885 struct da8xx_fb_par *par = arg;
910 lcd_blit(LOAD_DATA, par);
915 par->which_dma_channel_done = 0;
916 lcdc_write(par->dma_start,
918 lcdc_write(par->dma_end,
920 par->vsync_flag = 1;
921 wake_up_interruptible(&par->vsync_wait);
925 par->which_dma_channel_done = 1;
926 lcdc_write(par->dma_start,
928 lcdc_write(par->dma_end,
930 par->vsync_flag = 1;
931 wake_up_interruptible(&par->vsync_wait);
942 struct da8xx_fb_par *par = info->par;
1013 if (line_size * var->yres_virtual > par->vram_size)
1014 var->yres_virtual = par->vram_size / line_size;
1027 var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
1036 struct da8xx_fb_par *par;
1038 par = container_of(nb, struct da8xx_fb_par, freq_transition);
1040 if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) {
1041 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1043 da8xx_fb_calc_config_clk_divider(par, &par->mode);
1044 if (par->blank == FB_BLANK_UNBLANK)
1052 static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1054 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1056 return cpufreq_register_notifier(&par->freq_transition,
1060 static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1062 cpufreq_unregister_notifier(&par->freq_transition,
1070 struct da8xx_fb_par *par = info->par;
1074 lcd_da8xx_cpufreq_deregister(par);
1076 if (par->lcd_supply) {
1077 ret = regulator_disable(par->lcd_supply);
1103 struct da8xx_fb_par *par = info->par;
1118 par->vsync_flag = 0;
1119 ret = wait_event_interruptible_timeout(par->vsync_wait,
1120 par->vsync_flag != 0,
1121 par->vsync_timeout);
1169 struct da8xx_fb_par *par = info->par;
1172 if (par->blank == blank)
1175 par->blank = blank;
1180 if (par->lcd_supply) {
1181 ret = regulator_enable(par->lcd_supply);
1190 if (par->lcd_supply) {
1191 ret = regulator_disable(par->lcd_supply);
1214 struct da8xx_fb_par *par = fbi->par;
1234 par->dma_start = start;
1235 par->dma_end = end;
1236 spin_lock_irqsave(&par->lock_for_chan_update,
1238 if (par->which_dma_channel_done == 0) {
1239 lcdc_write(par->dma_start,
1241 lcdc_write(par->dma_end,
1243 } else if (par->which_dma_channel_done == 1) {
1244 lcdc_write(par->dma_start,
1246 lcdc_write(par->dma_end,
1249 spin_unlock_irqrestore(&par->lock_for_chan_update,
1259 struct da8xx_fb_par *par = info->par;
1266 fb_var_to_videomode(&par->mode, &info->var);
1268 par->cfg.bpp = info->var.bits_per_pixel;
1270 info->fix.visual = (par->cfg.bpp <= 8) ?
1272 info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8;
1274 ret = lcd_init(par, &par->cfg, &par->mode);
1276 dev_err(par->dev, "lcd init failed\n");
1280 par->dma_start = info->fix.smem_start +
1283 par->dma_end = par->dma_start +
1286 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1287 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1288 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1289 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1338 struct da8xx_fb_par *par;
1396 par = da8xx_fb_info->par;
1397 par->dev = &device->dev;
1398 par->lcdc_clk = tmp_lcdc_clk;
1399 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1401 par->lcd_supply = devm_regulator_get_optional(&device->dev, "lcd");
1402 if (IS_ERR(par->lcd_supply)) {
1403 if (PTR_ERR(par->lcd_supply) == -EPROBE_DEFER) {
1408 par->lcd_supply = NULL;
1410 ret = regulator_enable(par->lcd_supply);
1416 par->cfg = *lcd_cfg;
1421 par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp;
1423 par->vram_size = roundup(par->vram_size/8, ulcm);
1424 par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1426 par->vram_virt = dmam_alloc_coherent(par->dev,
1427 par->vram_size,
1428 &par->vram_phys,
1430 if (!par->vram_virt) {
1437 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1438 da8xx_fb_fix.smem_start = par->vram_phys;
1439 da8xx_fb_fix.smem_len = par->vram_size;
1442 par->dma_start = par->vram_phys;
1443 par->dma_end = par->dma_start + lcdc_info->yres *
1447 par->v_palette_base = dmam_alloc_coherent(par->dev, PALETTE_SIZE,
1448 &par->p_palette_base,
1450 if (!par->v_palette_base) {
1457 par->irq = platform_get_irq(device, 0);
1458 if (par->irq < 0) {
1472 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1479 da8xx_fb_info->cmap.len = par->palette_sz;
1488 init_waitqueue_head(&par->vsync_wait);
1489 par->vsync_timeout = HZ / 5;
1490 par->which_dma_channel_done = -1;
1491 spin_lock_init(&par->lock_for_chan_update);
1502 ret = lcd_da8xx_cpufreq_register(par);
1516 ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0,
1517 DRIVER_NAME, par);
1524 lcd_da8xx_cpufreq_deregister(par);
1609 struct da8xx_fb_par *par = info->par;
1613 if (par->lcd_supply) {
1614 ret = regulator_disable(par->lcd_supply);
1630 struct da8xx_fb_par *par = info->par;
1636 if (par->blank == FB_BLANK_UNBLANK) {
1639 if (par->lcd_supply) {
1640 ret = regulator_enable(par->lcd_supply);