Lines Matching refs:cinfo
380 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
381 static void WGen(const struct cirrusfb_info *cinfo,
383 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
384 static void AttrOn(const struct cirrusfb_info *cinfo);
385 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
386 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
387 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
388 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
391 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
420 static inline int is_laguna(const struct cirrusfb_info *cinfo)
422 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
450 struct cirrusfb_info *cinfo = info->par;
451 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
477 struct cirrusfb_info *cinfo = info->par;
483 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
484 cinfo->multiplexing = 0;
501 switch (cinfo->btype) {
506 cinfo->multiplexing = 1;
510 cinfo->multiplexing = 1;
520 cinfo->doubleVCLK = 0;
521 if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
523 cinfo->doubleVCLK = 1;
535 struct cirrusfb_info *cinfo = info->par;
625 if (!is_laguna(cinfo))
633 struct cirrusfb_info *cinfo = info->par;
636 assert(cinfo != NULL);
637 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
643 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
647 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
649 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
659 struct cirrusfb_info *cinfo = info->par;
661 u8 __iomem *regbase = cinfo->regbase;
696 bi = &cirrusfb_board_info[cinfo->btype];
734 if (cinfo->multiplexing) {
837 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
839 if (cinfo->multiplexing)
841 if (cinfo->doubleVCLK)
854 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
855 cinfo->btype == BT_SD64) {
864 if (is_laguna(cinfo)) {
865 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
866 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
869 if (cinfo->btype == BT_LAGUNAB) {
870 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
872 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
875 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
876 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
877 control = fb_readw(cinfo->laguna_mmio + 0x402);
878 threshold = fb_readw(cinfo->laguna_mmio + 0xea);
888 if ((cinfo->btype == BT_SD64) ||
889 (cinfo->btype == BT_ALPINE) ||
890 (cinfo->btype == BT_GD5480))
894 if (is_laguna(cinfo)) {
925 WGen(cinfo, VGA_MIS_W, tmp);
944 switch (cinfo->btype) {
953 cinfo->multiplexing ?
969 switch (cinfo->btype) {
997 WGen(cinfo, VGA_PEL_MSK, 0x01);
998 if (cinfo->multiplexing)
1000 WHDR(cinfo, 0x4a);
1003 WHDR(cinfo, 0);
1018 switch (cinfo->btype) {
1027 cinfo->multiplexing ?
1043 switch (cinfo->btype) {
1071 if (cinfo->multiplexing)
1073 WHDR(cinfo, 0x4a);
1076 WHDR(cinfo, 0);
1087 switch (cinfo->btype) {
1106 cinfo->doubleVCLK ? 0xa3 : 0xa7);
1131 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
1134 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1146 switch (cinfo->btype) {
1189 WHDR(cinfo, 0xc5);
1213 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1216 if (is_laguna(cinfo)) {
1240 AttrOn(cinfo);
1242 if (is_laguna(cinfo)) {
1244 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1245 fb_writew(format, cinfo->laguna_mmio + 0xc0);
1246 fb_writew(threshold, cinfo->laguna_mmio + 0xea);
1279 struct cirrusfb_info *cinfo = info->par;
1296 cinfo->pseudo_palette[regno] = v;
1301 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1318 struct cirrusfb_info *cinfo = info->par;
1337 if (!is_laguna(cinfo))
1338 cirrusfb_WaitBLT(cinfo->regbase);
1341 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
1342 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
1345 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1354 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1357 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1358 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
1359 if (is_laguna(cinfo))
1363 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1371 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1390 struct cirrusfb_info *cinfo = info->par;
1391 int current_mode = cinfo->blank_mode;
1410 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1411 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1432 vga_wgfx(cinfo->regbase, CL_GRE, val);
1434 cinfo->blank_mode = blank_mode;
1447 struct cirrusfb_info *cinfo = info->par;
1450 assert(cinfo != NULL);
1452 bi = &cirrusfb_board_info[cinfo->btype];
1455 switch (cinfo->btype) {
1457 WSFR(cinfo, 0x01);
1459 WSFR(cinfo, 0x51);
1463 WSFR2(cinfo, 0xff);
1468 WSFR(cinfo, 0x1f);
1470 WSFR(cinfo, 0x4f);
1475 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1478 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1482 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1486 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1506 if (cinfo->btype != BT_PICASSO4) {
1507 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1508 WGen(cinfo, CL_POS102, 0x01);
1509 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1511 if (cinfo->btype != BT_SD64)
1512 WGen(cinfo, CL_VSSM2, 0x01);
1515 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1518 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1521 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1523 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1525 switch (cinfo->btype) {
1527 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1535 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1539 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1540 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1545 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1547 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1549 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1553 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1555 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1559 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1561 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1563 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1565 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1568 if (cinfo->btype != BT_PICASSO4) {
1570 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1572 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1576 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1578 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1580 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1582 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1584 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1587 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1590 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1593 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1595 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1597 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1599 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1601 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1603 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1605 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1607 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1609 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1611 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
1612 is_laguna(cinfo))
1614 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1619 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1621 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1622 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1623 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1625 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1626 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1629 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1630 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1647 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1649 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1651 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1653 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1655 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1658 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1660 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1663 WHDR(cinfo, 0); /* Hidden DAC register: - */
1667 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1672 if (cinfo->btype == BT_PICASSO4)
1674 if (cinfo->btype == BT_ALPINE)
1676 if (cinfo->btype == BT_GD5480)
1678 if (cinfo->btype == BT_PICASSO) {
1680 WSFR(cinfo, 0xff);
1684 switch (cinfo->btype) {
1686 WSFR(cinfo, cinfo->SFR | 0x21);
1689 WSFR(cinfo, cinfo->SFR | 0x28);
1692 WSFR(cinfo, 0x6f);
1697 switch (cinfo->btype) {
1699 WSFR(cinfo, cinfo->SFR & 0xde);
1702 WSFR(cinfo, cinfo->SFR & 0xd7);
1705 WSFR(cinfo, 0x4f);
1720 struct cirrusfb_info *cinfo = info->par;
1722 if (!is_laguna(cinfo)) {
1723 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
1734 struct cirrusfb_info *cinfo = info->par;
1737 cinfo->pseudo_palette[region->color] : region->color;
1760 cirrusfb_RectFill(cinfo->regbase,
1773 struct cirrusfb_info *cinfo = info->par;
1801 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1812 struct cirrusfb_info *cinfo = info->par;
1820 else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
1837 cirrusfb_RectFill(cinfo->regbase,
1845 cirrusfb_RectFill(cinfo->regbase,
1866 struct cirrusfb_info *cinfo = info->par;
1868 if (is_laguna(cinfo)) {
1894 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
1928 struct cirrusfb_info *cinfo = info->par;
1930 if (cinfo->laguna_mmio == NULL)
1931 iounmap(cinfo->laguna_mmio);
1945 struct cirrusfb_info *cinfo = info->par;
1951 iounmap(cinfo->regbase);
1975 struct cirrusfb_info *cinfo = info->par;
1978 info->pseudo_palette = cinfo->pseudo_palette;
1985 if (noaccel || is_laguna(cinfo)) {
1993 if (cinfo->btype == BT_GD5480) {
2001 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2024 struct cirrusfb_info *cinfo = info->par;
2028 assert(cinfo->btype != BT_NONE);
2068 struct cirrusfb_info *cinfo = info->par;
2070 switch_monitor(cinfo, 0);
2074 cinfo->unmap(info);
2082 struct cirrusfb_info *cinfo;
2099 cinfo = info->par;
2100 cinfo->btype = (enum cirrus_board) ent->driver_data;
2104 (unsigned long long)pdev->resource[0].start, cinfo->btype);
2112 cinfo->regbase = NULL;
2113 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
2118 board_size = (cinfo->btype == BT_GD5480) ?
2119 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2146 cinfo->unmap = cirrusfb_pci_unmap;
2167 if (cinfo->laguna_mmio != NULL)
2168 iounmap(cinfo->laguna_mmio);
2204 struct cirrusfb_info *cinfo;
2252 cinfo = info->par;
2253 cinfo->btype = btype;
2256 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024)
2258 if (!cinfo->regbase) {
2274 cinfo->unmap = cirrusfb_zorro_unmap;
2282 vga_wseq(cinfo->regbase, CL_SEQR1F,
2301 iounmap(cinfo->regbase);
2406 static void WGen(const struct cirrusfb_info *cinfo,
2411 if (cinfo->btype == BT_PICASSO) {
2419 vga_w(cinfo->regbase, regofs + regnum, val);
2423 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2427 if (cinfo->btype == BT_PICASSO) {
2435 return vga_r(cinfo->regbase, regofs + regnum);
2439 static void AttrOn(const struct cirrusfb_info *cinfo)
2441 assert(cinfo != NULL);
2443 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2446 vga_w(cinfo->regbase, VGA_ATT_IW,
2447 vga_r(cinfo->regbase, VGA_ATT_R));
2450 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2451 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2454 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2463 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2467 if (is_laguna(cinfo))
2469 if (cinfo->btype == BT_PICASSO) {
2472 WGen(cinfo, VGA_PEL_MSK, 0x00);
2475 dummy = RGen(cinfo, VGA_PEL_IW);
2480 dummy = RGen(cinfo, VGA_PEL_MSK);
2482 dummy = RGen(cinfo, VGA_PEL_MSK);
2484 dummy = RGen(cinfo, VGA_PEL_MSK);
2486 dummy = RGen(cinfo, VGA_PEL_MSK);
2489 WGen(cinfo, VGA_PEL_MSK, val);
2492 if (cinfo->btype == BT_PICASSO) {
2494 dummy = RGen(cinfo, VGA_PEL_IW);
2499 WGen(cinfo, VGA_PEL_MSK, 0xff);
2505 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2508 assert(cinfo->regbase != NULL);
2509 cinfo->SFR = val;
2510 z_writeb(val, cinfo->regbase + 0x8000);
2515 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2520 assert(cinfo->regbase != NULL);
2521 cinfo->SFR = val;
2522 z_writeb(val, cinfo->regbase + 0x9000);
2527 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2533 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2535 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2536 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
2537 cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
2539 if (cinfo->btype == BT_PICASSO)
2541 vga_w(cinfo->regbase, data, red);
2542 vga_w(cinfo->regbase, data, green);
2543 vga_w(cinfo->regbase, data, blue);
2545 vga_w(cinfo->regbase, data, blue);
2546 vga_w(cinfo->regbase, data, green);
2547 vga_w(cinfo->regbase, data, red);
2553 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2558 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2560 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2561 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2562 if (cinfo->btype == BT_PICASSO)
2564 *red = vga_r(cinfo->regbase, data);
2565 *green = vga_r(cinfo->regbase, data);
2566 *blue = vga_r(cinfo->regbase, data);
2568 *blue = vga_r(cinfo->regbase, data);
2569 *green = vga_r(cinfo->regbase, data);
2570 *red = vga_r(cinfo->regbase, data);