Lines Matching refs:rinfo
41 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo);
99 static int radeon_apply_workarounds(struct radeonfb_info *rinfo)
104 if ((id->subsystem_vendor == rinfo->pdev->subsystem_vendor ) &&
105 (id->subsystem_device == rinfo->pdev->subsystem_device )) {
111 rinfo->pm_mode |= id->pm_mode_modifier;
114 rinfo->reinit_func = id->new_reinit_func;
122 static inline int radeon_apply_workarounds(struct radeonfb_info *rinfo)
130 static void radeon_pm_disable_dynamic_mode(struct radeonfb_info *rinfo)
135 if ((rinfo->family == CHIP_FAMILY_RV100) && (!rinfo->is_mobility)) {
136 if (rinfo->has_CRTC2) {
153 if (!rinfo->has_CRTC2) {
166 if (rinfo->family == CHIP_FAMILY_RV350) {
232 if (rinfo->is_mobility) {
249 else if (rinfo->family == CHIP_FAMILY_R300 ||
250 rinfo->family == CHIP_FAMILY_R350) {
261 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
275 if (rinfo->is_IGP) {
286 else if (rinfo->is_mobility) {
304 if (rinfo->is_mobility) {
331 static void radeon_pm_enable_dynamic_mode(struct radeonfb_info *rinfo)
336 if (!rinfo->has_CRTC2) {
351 if (rinfo->family == CHIP_FAMILY_RV350) {
421 if (rinfo->vram_width == 64) {
436 if (rinfo->family == CHIP_FAMILY_R300 || rinfo->family == CHIP_FAMILY_R350) {
473 if ((rinfo->family == CHIP_FAMILY_RV250 &&
475 ((rinfo->family == CHIP_FAMILY_RV100) &&
483 if ((rinfo->family == CHIP_FAMILY_RV200) ||
484 (rinfo->family == CHIP_FAMILY_RV250) ||
485 (rinfo->family == CHIP_FAMILY_RV280)) {
490 if (((rinfo->family == CHIP_FAMILY_RV200) ||
491 (rinfo->family == CHIP_FAMILY_RV250)) &&
501 if (((rinfo->family == CHIP_FAMILY_RV200) ||
502 (rinfo->family == CHIP_FAMILY_RV250)) &&
528 if (rinfo->is_mobility) {
550 static void OUTMC( struct radeonfb_info *rinfo, u8 indx, u32 value)
556 static u32 INMC(struct radeonfb_info *rinfo, u8 indx)
562 static void radeon_pm_save_regs(struct radeonfb_info *rinfo, int saving_for_d3)
564 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
565 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
566 rinfo->save_regs[2] = INPLL(MCLK_CNTL);
567 rinfo->save_regs[3] = INPLL(SCLK_CNTL);
568 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
569 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
570 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
571 rinfo->save_regs[7] = INPLL(MCLK_MISC);
572 rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
574 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
575 rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
576 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
577 rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
578 rinfo->save_regs[14] = INREG(BUS_CNTL1);
579 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
580 rinfo->save_regs[16] = INREG(AGP_CNTL);
581 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
582 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
583 rinfo->save_regs[19] = INREG(GPIOPAD_A);
584 rinfo->save_regs[20] = INREG(GPIOPAD_EN);
585 rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
586 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
587 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
588 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
589 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
590 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
591 rinfo->save_regs[27] = INREG(GPIO_MONID);
592 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
594 rinfo->save_regs[29] = INREG(SURFACE_CNTL);
595 rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
596 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
597 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
598 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
600 rinfo->save_regs[34] = INPLL(SCLK_MORE_CNTL);
601 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG);
602 rinfo->save_regs[36] = INREG(BUS_CNTL);
603 rinfo->save_regs[39] = INREG(RBBM_CNTL);
604 rinfo->save_regs[40] = INREG(DAC_CNTL);
605 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL);
606 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG);
607 rinfo->save_regs[38] = INREG(FCP_CNTL);
609 if (rinfo->is_mobility) {
610 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
611 rinfo->save_regs[43] = INPLL(pllSSPLL_CNTL);
612 rinfo->save_regs[44] = INPLL(pllSSPLL_REF_DIV);
613 rinfo->save_regs[45] = INPLL(pllSSPLL_DIV_0);
614 rinfo->save_regs[90] = INPLL(pllSS_INT_CNTL);
615 rinfo->save_regs[91] = INPLL(pllSS_TST_CNTL);
616 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL);
619 if (rinfo->family >= CHIP_FAMILY_RV200) {
620 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL);
621 rinfo->save_regs[46] = INREG(MC_CNTL);
622 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER);
623 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER);
624 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL);
625 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB);
626 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL);
627 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB);
628 rinfo->save_regs[53] = INREG(MC_DEBUG);
630 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL);
631 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL);
632 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC);
633 rinfo->save_regs[57] = INREG(FW_CNTL);
635 if (rinfo->family >= CHIP_FAMILY_R300) {
636 rinfo->save_regs[58] = INMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER);
637 rinfo->save_regs[59] = INMC(rinfo, ixR300_MC_IMP_CNTL);
638 rinfo->save_regs[60] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0);
639 rinfo->save_regs[61] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1);
640 rinfo->save_regs[62] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0);
641 rinfo->save_regs[63] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1);
642 rinfo->save_regs[64] = INMC(rinfo, ixR300_MC_BIST_CNTL_3);
643 rinfo->save_regs[65] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0);
644 rinfo->save_regs[66] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1);
645 rinfo->save_regs[67] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0);
646 rinfo->save_regs[68] = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1);
647 rinfo->save_regs[69] = INMC(rinfo, ixR300_MC_DEBUG_CNTL);
648 rinfo->save_regs[70] = INMC(rinfo, ixR300_MC_DLL_CNTL);
649 rinfo->save_regs[71] = INMC(rinfo, ixR300_MC_IMP_CNTL_0);
650 rinfo->save_regs[72] = INMC(rinfo, ixR300_MC_ELPIDA_CNTL);
651 rinfo->save_regs[96] = INMC(rinfo, ixR300_MC_READ_CNTL_CD);
653 rinfo->save_regs[59] = INMC(rinfo, ixMC_IMP_CNTL);
654 rinfo->save_regs[65] = INMC(rinfo, ixMC_CHP_IO_CNTL_A0);
655 rinfo->save_regs[66] = INMC(rinfo, ixMC_CHP_IO_CNTL_A1);
656 rinfo->save_regs[67] = INMC(rinfo, ixMC_CHP_IO_CNTL_B0);
657 rinfo->save_regs[68] = INMC(rinfo, ixMC_CHP_IO_CNTL_B1);
658 rinfo->save_regs[71] = INMC(rinfo, ixMC_IMP_CNTL_0);
661 rinfo->save_regs[73] = INPLL(pllMPLL_CNTL);
662 rinfo->save_regs[74] = INPLL(pllSPLL_CNTL);
663 rinfo->save_regs[75] = INPLL(pllMPLL_AUX_CNTL);
664 rinfo->save_regs[76] = INPLL(pllSPLL_AUX_CNTL);
665 rinfo->save_regs[77] = INPLL(pllM_SPLL_REF_FB_DIV);
666 rinfo->save_regs[78] = INPLL(pllAGP_PLL_CNTL);
667 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL);
669 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR);
670 rinfo->save_regs[82] = INREG(FP_GEN_CNTL);
671 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL);
672 rinfo->save_regs[84] = INREG(TMDS_CNTL);
673 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL);
674 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL);
675 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG);
676 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL);
677 rinfo->save_regs[89] = INPLL(pllP2PLL_REF_DIV);
678 rinfo->save_regs[92] = INPLL(pllPPLL_DIV_0);
679 rinfo->save_regs[93] = INPLL(pllPPLL_CNTL);
680 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL);
681 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL);
682 rinfo->save_regs[96] = INREG(HDP_DEBUG);
683 rinfo->save_regs[97] = INPLL(pllMDLL_CKO);
684 rinfo->save_regs[98] = INPLL(pllMDLL_RDCKA);
685 rinfo->save_regs[99] = INPLL(pllMDLL_RDCKB);
688 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
690 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
692 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
693 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
694 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
695 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
696 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
697 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
698 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
699 OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
700 if (rinfo->family == CHIP_FAMILY_RV350)
701 OUTPLL(SCLK_MORE_CNTL, rinfo->save_regs[34]);
703 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
704 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
705 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
706 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
707 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
708 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
710 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
711 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
712 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
713 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
714 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
715 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
716 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
717 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
718 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
719 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
720 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
722 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
723 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
724 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
725 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
726 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
727 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
728 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
729 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
730 OUTREG(GPIO_MONID, rinfo->save_regs[27]);
731 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
734 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
748 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
751 if (rinfo->family <= CHIP_FAMILY_RV280) {
753 __INPLL(rinfo, pllPIXCLKS_CNTL)
778 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
783 if (rinfo->family <= CHIP_FAMILY_RV280) {
822 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
863 if (rinfo->family <= CHIP_FAMILY_RV280)
963 if (rinfo->family <= CHIP_FAMILY_RV280) {
1060 static void radeon_pm_yclk_mclk_sync(struct radeonfb_info *rinfo)
1064 mc_chp_io_cntl_a1 = INMC( rinfo, ixMC_CHP_IO_CNTL_A1)
1066 mc_chp_io_cntl_b1 = INMC( rinfo, ixMC_CHP_IO_CNTL_B1)
1069 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1
1071 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1
1074 OUTMC( rinfo, ixMC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1075 OUTMC( rinfo, ixMC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1080 static void radeon_pm_yclk_mclk_sync_m10(struct radeonfb_info *rinfo)
1084 mc_chp_io_cntl_a1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1)
1086 mc_chp_io_cntl_b1 = INMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1)
1089 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1,
1091 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1,
1094 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_A1, mc_chp_io_cntl_a1);
1095 OUTMC( rinfo, ixR300_MC_CHP_IO_CNTL_B1, mc_chp_io_cntl_b1);
1100 static void radeon_pm_program_mode_reg(struct radeonfb_info *rinfo, u16 value,
1134 static void radeon_pm_m10_program_mode_wait(struct radeonfb_info *rinfo)
1147 static void radeon_pm_enable_dll(struct radeonfb_info *rinfo)
1194 static void radeon_pm_enable_dll_m10(struct radeonfb_info *rinfo)
1204 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1248 static void radeon_pm_full_reset_sdram(struct radeonfb_info *rinfo)
1269 if (rinfo->family == CHIP_FAMILY_RV350) {
1270 u32 sdram_mode_reg = rinfo->save_regs[35];
1292 radeon_pm_enable_dll_m10(rinfo);
1293 radeon_pm_yclk_mclk_sync_m10(rinfo);
1296 if (rinfo->of_node != NULL) {
1299 mrtable = of_get_property(rinfo->of_node, "ATY,MRT", &size);
1312 radeon_pm_m10_program_mode_wait(rinfo);
1330 else if (!rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV200) {
1342 radeon_pm_program_mode_reg(rinfo, 0x2002, 2);
1343 radeon_pm_program_mode_reg(rinfo, 0x0132, 2);
1344 radeon_pm_program_mode_reg(rinfo, 0x0032, 2);
1353 else if (rinfo->is_mobility && rinfo->family == CHIP_FAMILY_RV100) {
1364 radeon_pm_enable_dll(rinfo);
1367 radeon_pm_yclk_mclk_sync(rinfo);
1370 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1371 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1372 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1373 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1374 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1383 else if (rinfo->is_mobility) {
1397 radeon_pm_enable_dll(rinfo);
1400 radeon_pm_yclk_mclk_sync(rinfo);
1403 if (rinfo->family <= CHIP_FAMILY_RV250) {
1404 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1405 radeon_pm_program_mode_reg(rinfo, 0x2001, 1);
1406 radeon_pm_program_mode_reg(rinfo, 0x2002, 1);
1407 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1408 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1411 else if (rinfo->family == CHIP_FAMILY_RV280) {
1412 radeon_pm_program_mode_reg(rinfo, 0x2000, 1);
1413 radeon_pm_program_mode_reg(rinfo, 0x0132, 1);
1414 radeon_pm_program_mode_reg(rinfo, 0x0032, 1);
1435 static void radeon_pm_reset_pad_ctlr_strength(struct radeonfb_info *rinfo)
1460 static void radeon_pm_all_ppls_off(struct radeonfb_info *rinfo)
1474 static void radeon_pm_start_mclk_sclk(struct radeonfb_info *rinfo)
1485 radeon_pll_errata_after_index(rinfo);
1487 radeon_pll_errata_after_data(rinfo);
1491 tmp = (tmp & 0xff00fffful) | (rinfo->save_regs[77] & 0x00ff0000ul);
1511 tmp |= rinfo->save_regs[3] & SCLK_CNTL__SCLK_SRC_SEL_MASK;
1520 radeon_pll_errata_after_index(rinfo);
1522 radeon_pll_errata_after_data(rinfo);
1526 tmp = (tmp & 0xffff00fful) | (rinfo->save_regs[77] & 0x0000ff00ul);
1545 tmp |= rinfo->save_regs[2] & 0xffff;
1552 static void radeon_pm_m10_disable_spread_spectrum(struct radeonfb_info *rinfo)
1570 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);
1581 static void radeon_pm_m10_enable_lvds_spread_spectrum(struct radeonfb_info *rinfo)
1594 OUTPLL(pllSSPLL_CNTL, rinfo->save_regs[43] | 3);
1597 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44]);
1598 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45]);
1606 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90]);
1622 OUTPLL(pllSCLK_MORE_CNTL, rinfo->save_regs[34]);
1623 OUTPLL(pllSS_TST_CNTL, rinfo->save_regs[91]);
1636 static void radeon_pm_restore_pixel_pll(struct radeonfb_info *rinfo)
1641 radeon_pll_errata_after_index(rinfo);
1643 radeon_pll_errata_after_data(rinfo);
1650 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
1659 radeon_pll_errata_after_index(rinfo);
1661 radeon_pll_errata_after_data(rinfo);
1666 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
1686 radeon_pll_errata_after_index(rinfo);
1687 radeon_pll_errata_after_data(rinfo);
1690 static void radeon_pm_m10_reconfigure_mc(struct radeonfb_info *rinfo)
1692 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1693 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1694 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1696 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1697 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1698 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1699 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1700 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1701 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1702 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1704 OUTMC(rinfo, ixR300_MC_MC_INIT_WR_LAT_TIMER, rinfo->save_regs[58]);
1705 OUTMC(rinfo, ixR300_MC_IMP_CNTL, rinfo->save_regs[59]);
1706 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C0, rinfo->save_regs[60]);
1707 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_C1, rinfo->save_regs[61]);
1708 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D0, rinfo->save_regs[62]);
1709 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_D1, rinfo->save_regs[63]);
1710 OUTMC(rinfo, ixR300_MC_BIST_CNTL_3, rinfo->save_regs[64]);
1711 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A0, rinfo->save_regs[65]);
1712 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_A1, rinfo->save_regs[66]);
1713 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B0, rinfo->save_regs[67]);
1714 OUTMC(rinfo, ixR300_MC_CHP_IO_CNTL_B1, rinfo->save_regs[68]);
1715 OUTMC(rinfo, ixR300_MC_DEBUG_CNTL, rinfo->save_regs[69]);
1716 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1717 OUTMC(rinfo, ixR300_MC_IMP_CNTL_0, rinfo->save_regs[71]);
1718 OUTMC(rinfo, ixR300_MC_ELPIDA_CNTL, rinfo->save_regs[72]);
1719 OUTMC(rinfo, ixR300_MC_READ_CNTL_CD, rinfo->save_regs[96]);
1723 static void radeon_reinitialize_M10(struct radeonfb_info *rinfo)
1728 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1729 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1730 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1731 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1732 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1733 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1734 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1735 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1736 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1737 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1738 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1739 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1747 radeon_pm_reset_pad_ctlr_strength(rinfo);
1753 radeon_pm_all_ppls_off(rinfo);
1771 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
1772 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
1773 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
1776 tmp = rinfo->save_regs[1]
1781 OUTREG(PAD_CTLR_MISC, rinfo->save_regs[56]);
1782 OUTREG(FW_CNTL, rinfo->save_regs[57]);
1783 OUTREG(HDP_DEBUG, rinfo->save_regs[96]);
1784 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
1785 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
1786 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
1789 radeon_pm_m10_reconfigure_mc(rinfo);
1803 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
1806 tmp = rinfo->save_regs[2] & 0xff000000;
1855 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
1856 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
1857 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
1860 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
1861 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
1862 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
1863 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
1866 OUTMC(rinfo, ixR300_MC_DLL_CNTL, rinfo->save_regs[70]);
1869 OUTPLL(pllMDLL_RDCKA, rinfo->save_regs[98] | 0xff);
1875 OUTPLL(pllPLL_PWRMGT_CNTL, rinfo->save_regs[0]);
1892 radeon_pm_start_mclk_sclk(rinfo);
1895 radeon_pm_full_reset_sdram(rinfo);
1910 OUTREG(FP_GEN_CNTL, rinfo->save_regs[82]);
1911 OUTREG(FP2_GEN_CNTL, rinfo->save_regs[83]);
1914 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
1916 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
1918 OUTREG(DISP_OUTPUT_CNTL, rinfo->save_regs[86]);
1921 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
1922 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
1923 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
1927 writeb(0, rinfo->fb_base + i);
1934 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
1935 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
1938 radeon_pm_m10_disable_spread_spectrum(rinfo);
1939 radeon_pm_restore_pixel_pll(rinfo);
1945 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
1951 static void radeon_pm_m9p_reconfigure_mc(struct radeonfb_info *rinfo)
1953 OUTREG(MC_CNTL, rinfo->save_regs[46]);
1954 OUTREG(MC_INIT_GFX_LAT_TIMER, rinfo->save_regs[47]);
1955 OUTREG(MC_INIT_MISC_LAT_TIMER, rinfo->save_regs[48]);
1957 rinfo->save_regs[35] & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE);
1958 OUTREG(MC_TIMING_CNTL, rinfo->save_regs[49]);
1959 OUTREG(MC_READ_CNTL_AB, rinfo->save_regs[50]);
1960 OUTREG(MEM_REFRESH_CNTL, rinfo->save_regs[42]);
1961 OUTREG(MC_IOPAD_CNTL, rinfo->save_regs[51]);
1962 OUTREG(MC_DEBUG, rinfo->save_regs[53]);
1963 OUTREG(MC_CHIP_IO_OE_CNTL_AB, rinfo->save_regs[52]);
1965 OUTMC(rinfo, ixMC_IMP_CNTL, rinfo->save_regs[59] /*0x00f460d6*/);
1966 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, rinfo->save_regs[65] /*0xfecfa666*/);
1967 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, rinfo->save_regs[66] /*0x141555ff*/);
1968 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, rinfo->save_regs[67] /*0xfecfa666*/);
1969 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, rinfo->save_regs[68] /*0x141555ff*/);
1970 OUTMC(rinfo, ixMC_IMP_CNTL_0, rinfo->save_regs[71] /*0x00009249*/);
1972 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
1977 static void radeon_reinitialize_M9P(struct radeonfb_info *rinfo)
1982 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
1983 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
1984 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
1985 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
1986 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
1987 OUTREG(OV0_BASE_ADDR, rinfo->save_regs[80]);
1988 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
1989 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
1990 OUTREG(MPP_TB_CONFIG, rinfo->save_regs[37]);
1991 OUTREG(FCP_CNTL, rinfo->save_regs[38]);
1992 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
1994 OUTREG(DAC_CNTL, rinfo->save_regs[40]);
1998 radeon_pm_reset_pad_ctlr_strength(rinfo);
2004 radeon_pm_all_ppls_off(rinfo);
2021 OUTPLL(pllAGP_PLL_CNTL, rinfo->save_regs[78]);
2023 OUTREG(PAMAC0_DLY_CNTL, rinfo->save_regs[54]);
2024 OUTREG(PAMAC1_DLY_CNTL, rinfo->save_regs[55]);
2025 OUTREG(PAMAC2_DLY_CNTL, rinfo->save_regs[79]);
2027 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2028 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]); /* MacOS sets that to 0 !!! */
2029 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2031 tmp = rinfo->save_regs[1]
2036 OUTREG(FW_CNTL, rinfo->save_regs[57]);
2043 OUTPLL(pllCLK_PIN_CNTL, rinfo->save_regs[4]);
2046 tmp = rinfo->save_regs[2] & 0xff000000;
2085 OUTPLL(pllM_SPLL_REF_FB_DIV, rinfo->save_regs[77]);
2086 OUTPLL(pllMPLL_AUX_CNTL, rinfo->save_regs[75]);
2087 OUTPLL(pllSPLL_AUX_CNTL, rinfo->save_regs[76]);
2090 OUTPLL(pllPPLL_CNTL, rinfo->save_regs[93] | 0x3);
2091 OUTPLL(pllP2PLL_CNTL, rinfo->save_regs[8] | 0x3);
2094 OUTPLL(pllMPLL_CNTL, rinfo->save_regs[73] | 0x03);
2095 OUTPLL(pllSPLL_CNTL, rinfo->save_regs[74] | 0x03);
2104 tmp = rinfo->save_regs[0];
2121 radeon_pm_m9p_reconfigure_mc(rinfo);
2124 radeon_pm_start_mclk_sclk(rinfo);
2127 radeon_pm_full_reset_sdram(rinfo);
2142 OUTREG(TV_MASTER_CNTL, rinfo->save_regs[88]);
2143 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13] | 0x07000000);
2150 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2151 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2152 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2158 tmp |= rinfo->save_regs[34] & 0xffff0000;
2163 tmp |= rinfo->save_regs[34] & 0xffff0000;
2167 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11] &
2170 OUTREG(LVDS_PLL_CNTL, (rinfo->save_regs[12] & ~0xf0000) | 0x20000);
2175 writeb(0, rinfo->fb_base + i);
2178 OUTPLL(pllSSPLL_REF_DIV, rinfo->save_regs[44] /*0x3f */);
2179 OUTPLL(pllSSPLL_DIV_0, rinfo->save_regs[45] /*0x000081bb */);
2191 OUTPLL(pllSS_INT_CNTL, rinfo->save_regs[90] & ~3);/*0x0020300c*/
2195 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div);
2196 OUTPLL(pllPPLL_DIV_0, rinfo->save_regs[92]);
2203 OUTREG(GRPH_BUFFER_CNTL, rinfo->save_regs[94]);
2204 OUTREG(GRPH2_BUFFER_CNTL, rinfo->save_regs[95]);
2207 radeon_pm_m10_disable_spread_spectrum(rinfo);
2208 radeon_pm_restore_pixel_pll(rinfo);
2209 radeon_pm_m10_enable_lvds_spread_spectrum(rinfo);
2214 static void radeon_reinitialize_QW(struct radeonfb_info *rinfo)
2221 OUTREG(MC_AGP_LOCATION, rinfo->save_regs[32]);
2222 OUTREG(DISPLAY_BASE_ADDR, rinfo->save_regs[31]);
2223 OUTREG(CRTC2_DISPLAY_BASE_ADDR, rinfo->save_regs[33]);
2224 OUTREG(MC_FB_LOCATION, rinfo->save_regs[30]);
2225 OUTREG(BUS_CNTL, rinfo->save_regs[36]);
2226 OUTREG(RBBM_CNTL, rinfo->save_regs[39]);
2242 OUTREG(SURFACE_CNTL, rinfo->save_regs[29]);
2243 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2244 OUTREG(HOST_PATH_CNTL, rinfo->save_regs[41]);
2245 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2247 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A0, 0xf7bb4433);
2249 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B0, 0xf7bb4433);
2279 radeon_pll_errata_after_index(rinfo);
2281 radeon_pll_errata_after_data(rinfo);
2302 radeon_pll_errata_after_index(rinfo);
2304 radeon_pll_errata_after_data(rinfo);
2345 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x151550ff);
2347 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x151550ff);
2350 OUTMC(rinfo, ixMC_CHP_IO_CNTL_A1, 0x141550ff);
2352 OUTMC(rinfo, ixMC_CHP_IO_CNTL_B1, 0x141550ff);
2368 OUTMC(rinfo, ixMC_IMP_CNTL, 0x00f460d6);
2370 OUTMC(rinfo, ixMC_IMP_CNTL_0, 0x00009249);
2373 OUTREG(CNFG_MEMSIZE, rinfo->video_ram);
2375 radeon_pm_full_reset_sdram(rinfo);
2387 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2388 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2389 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2432 radeon_pll_errata_after_index(rinfo);
2434 radeon_pll_errata_after_data(rinfo);
2451 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
2456 radeon_pll_errata_after_index(rinfo);
2458 radeon_pll_errata_after_data(rinfo);
2461 radeon_pll_errata_after_index(rinfo);
2463 radeon_pll_errata_after_index(rinfo);
2464 radeon_pll_errata_after_data(rinfo);
2519 static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t state)
2524 pci_read_config_word(rinfo->pdev,
2525 rinfo->pdev->pm_cap + PCI_PM_CTRL,
2530 pci_write_config_word(rinfo->pdev,
2531 rinfo->pdev->pm_cap + PCI_PM_CTRL,
2535 rinfo->pdev->current_state = state;
2538 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2542 if (!rinfo->pdev->pm_cap)
2551 pci_name(rinfo->pdev));
2556 radeon_pm_disable_dynamic_mode(rinfo);
2559 radeon_pm_save_regs(rinfo, 0);
2563 if (rinfo->is_mobility) {
2565 radeon_pm_program_v2clk(rinfo);
2568 radeon_pm_disable_iopad(rinfo);
2571 radeon_pm_low_current(rinfo);
2574 radeon_pm_setup_for_suspend(rinfo);
2576 if (rinfo->family <= CHIP_FAMILY_RV280) {
2587 pci_disable_device(rinfo->pdev);
2588 pci_save_state(rinfo->pdev);
2593 radeonfb_whack_power_state(rinfo, PCI_D2);
2594 pci_platform_power_transition(rinfo->pdev, PCI_D2);
2597 pci_name(rinfo->pdev));
2599 if (rinfo->family <= CHIP_FAMILY_RV250) {
2601 radeon_pm_full_reset_sdram(rinfo);
2604 radeon_pm_restore_regs(rinfo);
2607 radeon_pm_restore_regs(rinfo);
2609 radeon_pm_full_reset_sdram(rinfo);
2618 struct radeonfb_info *rinfo = info->par;
2644 radeonfb_engine_reset(rinfo);
2649 radeon_screen_blank(rinfo, FB_BLANK_POWERDOWN, 1);
2652 rinfo->asleep = 1;
2653 rinfo->lock_blank = 1;
2654 del_timer_sync(&rinfo->lvds_timer);
2667 if (rinfo->pm_mode & radeon_pm_off) {
2674 radeon_pm_disable_dynamic_mode(rinfo);
2676 radeon_pm_save_regs(rinfo, 1);
2678 if (rinfo->is_mobility && !(rinfo->pm_mode & radeon_pm_d2)) {
2692 if (rinfo->pm_mode & radeon_pm_d2)
2693 radeon_set_suspend(rinfo, 1);
2718 static int radeon_check_power_loss(struct radeonfb_info *rinfo)
2720 return rinfo->save_regs[4] != INPLL(CLK_PIN_CNTL) ||
2721 rinfo->save_regs[2] != INPLL(MCLK_CNTL) ||
2722 rinfo->save_regs[3] != INPLL(SCLK_CNTL);
2729 struct radeonfb_info *rinfo = info->par;
2735 if (rinfo->no_schedule) {
2750 if ((rinfo->pm_mode & radeon_pm_off) && radeon_check_power_loss(rinfo)) {
2751 if (rinfo->reinit_func != NULL)
2752 rinfo->reinit_func(rinfo);
2764 else if (rinfo->pm_mode & radeon_pm_d2)
2765 radeon_set_suspend(rinfo, 0);
2767 rinfo->asleep = 0;
2772 radeon_write_mode (rinfo, &rinfo->state, 1);
2774 radeonfb_engine_init (rinfo);
2783 rinfo->lock_blank = 0;
2784 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 1);
2796 if (rinfo->dynclk == 1)
2797 radeon_pm_enable_dynamic_mode(rinfo);
2798 else if (rinfo->dynclk == 0)
2799 radeon_pm_disable_dynamic_mode(rinfo);
2821 struct radeonfb_info *rinfo = data;
2823 rinfo->no_schedule = 1;
2824 pci_restore_state(rinfo->pdev);
2825 radeonfb_pci_resume(rinfo->pdev);
2826 rinfo->no_schedule = 0;
2832 void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep)
2835 if (rinfo->family == CHIP_FAMILY_RS480)
2836 rinfo->dynclk = -1;
2838 rinfo->dynclk = dynclk;
2840 if (rinfo->dynclk == 1) {
2841 radeon_pm_enable_dynamic_mode(rinfo);
2843 } else if (rinfo->dynclk == 0) {
2844 radeon_pm_disable_dynamic_mode(rinfo);
2856 if (machine_is(powermac) && rinfo->of_node) {
2857 if (rinfo->is_mobility && rinfo->pdev->pm_cap &&
2858 rinfo->family <= CHIP_FAMILY_RV250)
2859 rinfo->pm_mode |= radeon_pm_d2;
2865 if (of_node_name_eq(rinfo->of_node, "ATY,JasperParent") ||
2866 of_node_name_eq(rinfo->of_node, "ATY,SnowyParent")) {
2867 rinfo->reinit_func = radeon_reinitialize_M10;
2868 rinfo->pm_mode |= radeon_pm_off;
2871 if (!strcmp(rinfo->of_node->name, "ATY,BlueStoneParent")) {
2872 rinfo->reinit_func = radeon_reinitialize_QW;
2873 rinfo->pm_mode |= radeon_pm_off;
2876 if (of_node_name_eq(rinfo->of_node, "ATY,ViaParent")) {
2877 rinfo->reinit_func = radeon_reinitialize_M9P;
2878 rinfo->pm_mode |= radeon_pm_off;
2886 if (rinfo->pm_mode != radeon_pm_none) {
2887 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1);
2894 pmac_set_early_video_resume(radeonfb_early_resume, rinfo);
2913 radeon_apply_workarounds(rinfo);
2918 rinfo->pm_mode |= radeon_pm_d2;
2922 void radeonfb_pm_exit(struct radeonfb_info *rinfo)
2925 if (rinfo->pm_mode != radeon_pm_none)