Lines Matching refs:rinfo
280 void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
282 if (rinfo->no_schedule || oops_in_progress)
288 void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo)
290 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */
295 void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo)
297 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
299 _radeon_msleep(rinfo, 5);
301 if (rinfo->errata & CHIP_ERRATA_R300_CG) {
311 void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask)
316 spin_lock_irqsave(&rinfo->reg_lock, flags);
321 spin_unlock_irqrestore(&rinfo->reg_lock, flags);
324 u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
329 radeon_pll_errata_after_index(rinfo);
331 radeon_pll_errata_after_data(rinfo);
335 void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val)
338 radeon_pll_errata_after_index(rinfo);
340 radeon_pll_errata_after_data(rinfo);
343 void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
348 tmp = __INPLL(rinfo, index);
351 __OUTPLL(rinfo, index, tmp);
354 void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries)
366 void radeon_engine_flush(struct radeonfb_info *rinfo)
377 _radeon_fifo_wait(rinfo, 64);
388 void _radeon_engine_idle(struct radeonfb_info *rinfo)
393 _radeon_fifo_wait(rinfo, 64);
397 radeon_engine_flush(rinfo);
407 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
409 if (!rinfo->bios_seg)
411 pci_unmap_rom(dev, rinfo->bios_seg);
414 static int radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
437 pci_name(rinfo->pdev));
441 rinfo->bios_seg = rom;
447 pci_name(rinfo->pdev), BIOS_IN16(0));
479 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
499 rinfo->fp_bios_start = BIOS_IN16(0x48);
503 rinfo->bios_seg = NULL;
504 radeon_unmap_ROM(rinfo, dev);
509 static int radeon_find_mem_vbios(struct radeonfb_info *rinfo)
532 rinfo->bios_seg = rom_base;
533 rinfo->fp_bios_start = BIOS_IN16(0x48);
544 static int radeon_read_xtal_OF(struct radeonfb_info *rinfo)
546 struct device_node *dp = rinfo->of_node;
557 rinfo->pll.ref_clk = (*val) / 10;
561 rinfo->pll.sclk = (*val) / 10;
565 rinfo->pll.mclk = (*val) / 10;
574 static int radeon_probe_pll_params(struct radeonfb_info *rinfo)
643 radeon_pll_errata_after_index(rinfo);
697 rinfo->pll.ref_clk = xtal;
698 rinfo->pll.ref_div = ref_div;
699 rinfo->pll.sclk = sclk;
700 rinfo->pll.mclk = mclk;
708 static void radeon_get_pllinfo(struct radeonfb_info *rinfo)
715 switch (rinfo->chipset) {
718 rinfo->pll.ppll_max = 35000;
719 rinfo->pll.ppll_min = 12000;
720 rinfo->pll.mclk = 23000;
721 rinfo->pll.sclk = 23000;
722 rinfo->pll.ref_clk = 2700;
729 rinfo->pll.ppll_max = 35000;
730 rinfo->pll.ppll_min = 12000;
731 rinfo->pll.mclk = 27500;
732 rinfo->pll.sclk = 27500;
733 rinfo->pll.ref_clk = 2700;
739 rinfo->pll.ppll_max = 35000;
740 rinfo->pll.ppll_min = 12000;
741 rinfo->pll.mclk = 25000;
742 rinfo->pll.sclk = 25000;
743 rinfo->pll.ref_clk = 2700;
749 rinfo->pll.ppll_max = 40000;
750 rinfo->pll.ppll_min = 20000;
751 rinfo->pll.mclk = 27000;
752 rinfo->pll.sclk = 27000;
753 rinfo->pll.ref_clk = 2700;
760 rinfo->pll.ppll_max = 35000;
761 rinfo->pll.ppll_min = 12000;
762 rinfo->pll.mclk = 16600;
763 rinfo->pll.sclk = 16600;
764 rinfo->pll.ref_clk = 2700;
767 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
774 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
784 if (!force_measure_pll && rinfo->bios_seg) {
785 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
787 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
788 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
789 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
790 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
791 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
792 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
802 if (radeon_probe_pll_params(rinfo) == 0) {
818 if (rinfo->pll.mclk == 0)
819 rinfo->pll.mclk = 20000;
820 if (rinfo->pll.sclk == 0)
821 rinfo->pll.sclk = 20000;
824 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
825 rinfo->pll.ref_div,
826 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
827 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
828 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
833 struct radeonfb_info *rinfo = info->par;
838 if (radeon_match_mode(rinfo, &v, var))
916 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
924 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
949 struct radeonfb_info *rinfo = info->par;
955 if (rinfo->asleep)
968 struct radeonfb_info *rinfo = info->par;
980 if (!rinfo->is_mobility)
1017 if (!rinfo->is_mobility)
1037 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
1043 if (rinfo->lock_blank)
1072 switch (rinfo->mon1_type) {
1084 del_timer_sync(&rinfo->lvds_timer);
1088 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
1095 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1096 rinfo->init_state.lvds_gen_cntl |=
1099 radeon_msleep(rinfo->panel_info.pwr_delay);
1103 rinfo->pending_lvds_gen_cntl = target_val;
1104 mod_timer(&rinfo->lvds_timer,
1106 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1121 if (rinfo->is_mobility || rinfo->is_IGP)
1129 rinfo->pending_lvds_gen_cntl = val;
1130 mod_timer(&rinfo->lvds_timer,
1132 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1133 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1134 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1135 if (rinfo->is_mobility || rinfo->is_IGP)
1150 struct radeonfb_info *rinfo = info->par;
1152 if (rinfo->asleep)
1155 return radeon_screen_blank(rinfo, blank, 0);
1160 struct radeonfb_info *rinfo)
1172 rinfo->palette[regno].red = red;
1173 rinfo->palette[regno].green = green;
1174 rinfo->palette[regno].blue = blue;
1179 if (!rinfo->asleep) {
1182 if (rinfo->bpp == 16) {
1185 if (rinfo->depth == 16 && regno > 63)
1187 if (rinfo->depth == 15 && regno > 31)
1193 if (rinfo->depth == 16) {
1196 (rinfo->palette[regno>>1].red << 16) |
1198 (rinfo->palette[regno>>1].blue));
1199 green = rinfo->palette[regno<<1].green;
1203 if (rinfo->depth != 16 || regno < 32) {
1210 u32 *pal = rinfo->info->pseudo_palette;
1211 switch (rinfo->depth) {
1234 struct radeonfb_info *rinfo = info->par;
1238 if (!rinfo->asleep) {
1239 if (rinfo->is_mobility) {
1246 if (rinfo->has_CRTC2) {
1253 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1255 if (!rinfo->asleep && rinfo->is_mobility)
1263 struct radeonfb_info *rinfo = info->par;
1268 if (!rinfo->asleep) {
1269 if (rinfo->is_mobility) {
1276 if (rinfo->has_CRTC2) {
1298 rinfo);
1303 if (!rinfo->asleep && rinfo->is_mobility)
1309 static void radeon_save_state (struct radeonfb_info *rinfo,
1340 radeon_pll_errata_after_index(rinfo);
1346 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1353 if (rinfo->is_mobility) {
1370 radeon_pll_errata_after_index(rinfo);
1371 radeon_pll_errata_after_data(rinfo);
1388 radeon_pll_errata_after_index(rinfo);
1389 radeon_pll_errata_after_data(rinfo);
1392 if (IS_R300_VARIANT(rinfo) ||
1393 rinfo->family == CHIP_FAMILY_RS300 ||
1394 rinfo->family == CHIP_FAMILY_RS400 ||
1395 rinfo->family == CHIP_FAMILY_RS480) {
1445 struct radeonfb_info *rinfo = from_timer(rinfo, t, lvds_timer);
1449 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1456 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1460 int primary_mon = PRIMARY_MONITOR(rinfo);
1466 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1493 radeon_write_pll_regs(rinfo, mode);
1509 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1520 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1555 while (rinfo->has_CRTC2) {
1566 if (rinfo->family == CHIP_FAMILY_R200 || IS_R300_VARIANT(rinfo)) {
1588 if (freq > rinfo->pll.ppll_max)
1589 freq = rinfo->pll.ppll_max;
1590 if (freq*12 < rinfo->pll.ppll_min)
1591 freq = rinfo->pll.ppll_min / 12;
1593 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1602 if (pll_output_freq >= rinfo->pll.ppll_min &&
1603 pll_output_freq <= rinfo->pll.ppll_max)
1614 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1624 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1627 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1628 rinfo->pll.ref_clk);
1629 regs->ppll_ref_div = rinfo->pll.ref_div;
1639 struct radeonfb_info *rinfo = info->par;
1651 int primary_mon = PRIMARY_MONITOR(rinfo);
1678 if (rinfo->panel_info.xres < mode->xres)
1679 mode->xres = rinfo->panel_info.xres;
1680 if (rinfo->panel_info.yres < mode->yres)
1681 mode->yres = rinfo->panel_info.yres;
1683 hTotal = mode->xres + rinfo->panel_info.hblank;
1684 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1685 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1687 vTotal = mode->yres + rinfo->panel_info.vblank;
1688 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1689 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1691 h_sync_pol = !rinfo->panel_info.hAct_high;
1692 v_sync_pol = !rinfo->panel_info.vAct_high;
1694 pixClock = 100000000 / rinfo->panel_info.clock;
1696 if (rinfo->panel_info.use_bios_dividers) {
1698 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1699 (rinfo->panel_info.post_divider << 16);
1700 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1736 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1768 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1772 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1816 rinfo->bpp = mode->bits_per_pixel;
1817 rinfo->depth = depth;
1827 radeon_calc_pll_regs(rinfo, newmode, freq);
1829 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1834 if (mode->xres > rinfo->panel_info.xres)
1835 mode->xres = rinfo->panel_info.xres;
1836 if (mode->yres > rinfo->panel_info.yres)
1837 mode->yres = rinfo->panel_info.yres;
1839 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1841 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1844 if (mode->xres != rinfo->panel_info.xres) {
1846 rinfo->panel_info.xres);
1857 if (mode->yres != rinfo->panel_info.yres) {
1859 rinfo->panel_info.yres);
1869 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1883 if (IS_R300_VARIANT(rinfo) ||
1884 (rinfo->family == CHIP_FAMILY_R200)) {
1893 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1894 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1895 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1896 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1906 if (IS_R300_VARIANT(rinfo) ||
1907 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1914 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1916 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1918 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1920 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1925 if (!rinfo->asleep) {
1926 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1927 radeon_write_mode (rinfo, newmode, 0);
1930 radeonfb_engine_init (rinfo);
1934 info->fix.line_length = rinfo->pitch*64;
1938 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1943 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1944 rinfo->depth, info->fix.line_length);
1968 static int radeon_set_fbinfo(struct radeonfb_info *rinfo)
1970 struct fb_info *info = rinfo->info;
1972 info->par = rinfo;
1973 info->pseudo_palette = rinfo->pseudo_palette;
1980 info->screen_base = rinfo->fb_base;
1981 info->screen_size = rinfo->mapped_vram;
1983 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1984 info->fix.smem_start = rinfo->fb_base_phys;
1985 info->fix.smem_len = rinfo->video_ram;
1992 info->fix.mmio_start = rinfo->mmio_base_phys;
2017 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
2025 if (rinfo->has_CRTC2) {
2043 rinfo->fb_local_base = aper_base;
2046 rinfo->fb_local_base = 0;
2067 if (rinfo->has_CRTC2)
2072 if (rinfo->has_CRTC2)
2081 if (rinfo->has_CRTC2)
2092 static void radeon_identify_vram(struct radeonfb_info *rinfo)
2097 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2098 (rinfo->family == CHIP_FAMILY_RS200) ||
2099 (rinfo->family == CHIP_FAMILY_RS300) ||
2100 (rinfo->family == CHIP_FAMILY_RC410) ||
2101 (rinfo->family == CHIP_FAMILY_RS400) ||
2102 (rinfo->family == CHIP_FAMILY_RS480) ) {
2115 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2116 (rinfo->family == CHIP_FAMILY_RS200)) {
2128 rinfo->video_ram = tmp & CNFG_MEMSIZE_MASK;
2134 if (rinfo->video_ram == 0) {
2135 switch (rinfo->pdev->device) {
2138 rinfo->video_ram = 8192 * 1024;
2149 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2151 rinfo->vram_ddr = 1;
2153 rinfo->vram_ddr = 0;
2156 if (IS_R300_VARIANT(rinfo)) {
2159 case 0: rinfo->vram_width = 64; break;
2160 case 1: rinfo->vram_width = 128; break;
2161 case 2: rinfo->vram_width = 256; break;
2162 default: rinfo->vram_width = 128; break;
2164 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2165 (rinfo->family == CHIP_FAMILY_RS100) ||
2166 (rinfo->family == CHIP_FAMILY_RS200)){
2168 rinfo->vram_width = 32;
2170 rinfo->vram_width = 64;
2173 rinfo->vram_width = 128;
2175 rinfo->vram_width = 64;
2183 pci_name(rinfo->pdev),
2184 rinfo->video_ram / 1024,
2185 rinfo->vram_ddr ? "DDR" : "SDRAM",
2186 rinfo->vram_width);
2205 struct radeonfb_info *rinfo = info->par;
2207 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2217 struct radeonfb_info *rinfo = info->par;
2219 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2262 struct radeonfb_info *rinfo;
2282 rinfo = info->par;
2283 rinfo->info = info;
2284 rinfo->pdev = pdev;
2286 spin_lock_init(&rinfo->reg_lock);
2287 timer_setup(&rinfo->lvds_timer, radeon_lvds_timer_func, 0);
2292 snprintf(rinfo->name, sizeof(rinfo->name),
2295 snprintf(rinfo->name, sizeof(rinfo->name),
2298 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2299 rinfo->chipset = pdev->device;
2300 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2301 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2302 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2305 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2306 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2316 pci_name(rinfo->pdev));
2323 pci_name(rinfo->pdev));
2328 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2329 if (!rinfo->mmio_base) {
2331 pci_name(rinfo->pdev));
2336 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2341 rinfo->errata = 0;
2342 if (rinfo->family == CHIP_FAMILY_R300 &&
2345 rinfo->errata |= CHIP_ERRATA_R300_CG;
2347 if (rinfo->family == CHIP_FAMILY_RV200 ||
2348 rinfo->family == CHIP_FAMILY_RS200)
2349 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2351 if (rinfo->family == CHIP_FAMILY_RV100 ||
2352 rinfo->family == CHIP_FAMILY_RS100 ||
2353 rinfo->family == CHIP_FAMILY_RS200)
2354 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2360 rinfo->of_node = pci_device_to_OF_node(pdev);
2361 if (rinfo->of_node == NULL)
2363 pci_name(rinfo->pdev));
2371 fixup_memory_mappings(rinfo);
2375 radeon_identify_vram(rinfo);
2377 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2380 rinfo->fb_base = ioremap_wc(rinfo->fb_base_phys,
2381 rinfo->mapped_vram);
2382 } while (rinfo->fb_base == NULL &&
2383 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2385 if (rinfo->fb_base == NULL) {
2387 pci_name(rinfo->pdev));
2392 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2393 rinfo->mapped_vram/1024);
2406 if (!rinfo->is_mobility)
2407 radeon_map_ROM(rinfo, pdev);
2416 if (rinfo->bios_seg == NULL)
2417 radeon_find_mem_vbios(rinfo);
2423 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2424 radeon_map_ROM(rinfo, pdev);
2427 radeon_get_pllinfo(rinfo);
2431 radeon_create_i2c_busses(rinfo);
2435 radeon_set_fbinfo (rinfo);
2438 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2441 radeon_check_modes(rinfo, mode_option);
2444 if (rinfo->mon1_EDID)
2445 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2447 if (rinfo->mon2_EDID)
2448 err |= sysfs_create_bin_file(&rinfo->pdev->dev.kobj,
2457 radeon_save_state (rinfo, &rinfo->init_state);
2458 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2465 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2467 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2475 pci_name(rinfo->pdev));
2480 rinfo->wc_cookie = arch_phys_wc_add(rinfo->fb_base_phys,
2481 rinfo->video_ram);
2484 radeonfb_bl_init(rinfo);
2486 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2488 if (rinfo->bios_seg)
2489 radeon_unmap_ROM(rinfo, pdev);
2494 iounmap(rinfo->fb_base);
2496 kfree(rinfo->mon1_EDID);
2497 kfree(rinfo->mon2_EDID);
2498 if (rinfo->mon1_modedb)
2499 fb_destroy_modedb(rinfo->mon1_modedb);
2502 radeon_delete_i2c_busses(rinfo);
2504 if (rinfo->bios_seg)
2505 radeon_unmap_ROM(rinfo, pdev);
2506 iounmap(rinfo->mmio_base);
2523 struct radeonfb_info *rinfo = info->par;
2525 if (!rinfo)
2528 radeonfb_pm_exit(rinfo);
2530 if (rinfo->mon1_EDID)
2531 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2532 if (rinfo->mon2_EDID)
2533 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2535 del_timer_sync(&rinfo->lvds_timer);
2536 arch_phys_wc_del(rinfo->wc_cookie);
2539 radeonfb_bl_exit(rinfo);
2541 iounmap(rinfo->mmio_base);
2542 iounmap(rinfo->fb_base);
2547 kfree(rinfo->mon1_EDID);
2548 kfree(rinfo->mon2_EDID);
2549 if (rinfo->mon1_modedb)
2550 fb_destroy_modedb(rinfo->mon1_modedb);
2552 radeon_delete_i2c_busses(rinfo);