Lines Matching defs:newmode
1641 struct radeon_regs *newmode;
1655 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1656 if (!newmode)
1698 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1700 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1732 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1736 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1737 newmode->crtc_more_cntl &= 0xfffffff0;
1740 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1742 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1744 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1747 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1751 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1754 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1757 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1760 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1763 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1772 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1774 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1776 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1783 newmode->surface_cntl = 0;
1793 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1794 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1798 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1799 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1806 newmode->surf_lower_bound[i] = 0;
1807 newmode->surf_upper_bound[i] = 0x1f;
1808 newmode->surf_info[i] = 0;
1812 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1814 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1823 newmode->clk_cntl_index = 0x300;
1827 radeon_calc_pll_regs(rinfo, newmode, freq);
1829 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1839 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1841 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1847 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1848 (newmode->fp_horz_stretch &
1851 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1855 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1860 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1861 (newmode->fp_vert_stretch &
1863 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1867 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1869 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1879 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1885 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1887 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1889 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1891 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1893 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1894 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1895 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1896 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1899 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1900 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1903 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1904 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1908 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1910 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1911 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1914 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1916 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1918 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1920 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1926 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1927 radeon_write_mode (rinfo, newmode, 0);
1947 kfree(newmode);