Lines Matching refs:pll
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
120 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll)
127 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
128 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
130 ras_multiplier = pll->xclkmaxrasdelay;
136 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */
142 if (pll->xres != 0) {
146 divider = divider * pll->xres & ~7;
149 ras_divider = ras_divider * pll->xres & ~7;
160 tmp = ((multiplier * pll->fifo_size) << vshift) / divider;
173 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider -
184 dsp_on = dsp_on + (tmp * 2) + (pll->xclkpagefaultdelay << xshift);
200 pll->dsp_on_off = (dsp_on << 16) + dsp_off;
201 pll->dsp_config = (dsp_precision << 20) | (pll->dsp_loop_latency << 16) | dsp_xclks;
204 __func__, pll->dsp_config, pll->dsp_on_off);
209 static int aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll)
216 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per;
221 pll->vclk_post_div = (q < 128*8);
222 pll->vclk_post_div += (q < 64*8);
223 pll->vclk_post_div += (q < 32*8);
225 pll->vclk_post_div_real = aty_postdividers[pll->vclk_post_div];
226 // pll->vclk_post_div <<= 6;
227 pll->vclk_fb_div = q * pll->vclk_post_div_real / 8;
228 pllvclk = (1000000 * 2 * pll->vclk_fb_div) /
229 (par->ref_clk_per * pll->pll_ref_div);
232 __func__, pllvclk, pllvclk / pll->vclk_post_div_real);
234 pll->pll_vclk_cntl = 0x03; /* VCLK = PLL_VCLK/VCLKx_POST */
238 int ecp = pllvclk / pll->vclk_post_div_real;
245 pll->pll_vclk_cntl |= ecp_div << 4;
251 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll)
256 if ((err = aty_valid_pll_ct(info, vclk_per, &pll->ct)))
258 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct)))
260 /*aty_calc_pll_ct(info, &pll->ct);*/
264 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll)
268 ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / 2;
270 if(pll->ct.xres > 0) {
272 ret /= pll->ct.xres;
281 void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll)
292 pll->ct.pll_ext_cntl, pll->ct.pll_gen_cntl, pll->ct.pll_vclk_cntl);
296 par->clk_wr_offset, pll->ct.vclk_fb_div,
297 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real);
314 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
320 tmp |= ((pll->ct.vclk_post_div & 0x03U) << tmp2);
327 tmp |= pll->ct.pll_ext_cntl;
332 aty_st_pll_ct(tmp, (pll->ct.vclk_fb_div & 0xFFU), par);
334 aty_st_pll_ct(PLL_GEN_CNTL, (pll->ct.pll_gen_cntl & (~(PLL_OVERRIDE | PLL_MCLK_RST))) | OSC_EN, par);
337 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl & ~(PLL_VCLK_RST), par);
340 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
341 aty_st_pll_ct(PLL_VCLK_CNTL, pll->ct.pll_vclk_cntl, par);
359 aty_st_le32(DSP_CONFIG, pll->ct.dsp_config, par);
360 aty_st_le32(DSP_ON_OFF, pll->ct.dsp_on_off, par);
377 static void aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll)
384 pll->ct.vclk_post_div = (aty_ld_pll_ct(VCLK_POST_DIV, par) >> tmp) & 0x03U;
386 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par) & 0x0FU;
387 pll->ct.vclk_fb_div = aty_ld_pll_ct(VCLK0_FB_DIV + clock, par) & 0xFFU;
388 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
389 pll->ct.mclk_fb_div = aty_ld_pll_ct(MCLK_FB_DIV, par);
391 pll->ct.pll_gen_cntl = aty_ld_pll_ct(PLL_GEN_CNTL, par);
392 pll->ct.pll_vclk_cntl = aty_ld_pll_ct(PLL_VCLK_CNTL, par);
395 pll->ct.dsp_config = aty_ld_le32(DSP_CONFIG, par);
396 pll->ct.dsp_on_off = aty_ld_le32(DSP_ON_OFF, par);
400 static int aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll)
409 pll->ct.pll_ext_cntl = aty_ld_pll_ct(PLL_EXT_CNTL, par);
410 pll->ct.xclk_post_div = pll->ct.pll_ext_cntl & 0x07;
411 pll->ct.xclk_ref_div = 1;
412 switch (pll->ct.xclk_post_div) {
417 pll->ct.xclk_ref_div = 3;
418 pll->ct.xclk_post_div = 0;
422 printk(KERN_CRIT "atyfb: Unsupported xclk source: %d.\n", pll->ct.xclk_post_div);
425 pll->ct.mclk_fb_mult = 2;
426 if(pll->ct.pll_ext_cntl & PLL_MFB_TIMES_4_2B) {
427 pll->ct.mclk_fb_mult = 4;
428 pll->ct.xclk_post_div -= 1;
433 __func__, pll->ct.mclk_fb_mult, pll->ct.xclk_post_div);
439 pll->ct.xclkpagefaultdelay = ((memcntl & 0xc00) >> 10) + ((memcntl & 0x1000) >> 12) + trp + 2;
440 pll->ct.xclkmaxrasdelay = ((memcntl & 0x70000) >> 16) + trp + 2;
443 pll->ct.fifo_size = 32;
445 pll->ct.fifo_size = 24;
446 pll->ct.xclkpagefaultdelay += 2;
447 pll->ct.xclkmaxrasdelay += 3;
453 pll->ct.dsp_loop_latency = 10;
455 pll->ct.dsp_loop_latency = 8;
456 pll->ct.xclkpagefaultdelay += 2;
462 pll->ct.dsp_loop_latency = 9;
464 pll->ct.dsp_loop_latency = 8;
465 pll->ct.xclkpagefaultdelay += 1;
470 pll->ct.dsp_loop_latency = 11;
472 pll->ct.dsp_loop_latency = 10;
473 pll->ct.xclkpagefaultdelay += 1;
477 pll->ct.dsp_loop_latency = 8;
478 pll->ct.xclkpagefaultdelay += 3;
481 pll->ct.dsp_loop_latency = 11;
482 pll->ct.xclkpagefaultdelay += 3;
486 if (pll->ct.xclkmaxrasdelay <= pll->ct.xclkpagefaultdelay)
487 pll->ct.xclkmaxrasdelay = pll->ct.xclkpagefaultdelay + 1;
496 pll->ct.dsp_loop_latency = (dsp_config & DSP_LOOP_LATENCY) >> 16;
505 pll->ct.fifo_size = 32;
507 pll->ct.fifo_size = 24;
514 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
516 pll->ct.xclk_post_div_real = aty_postdividers[pll_ext_cntl & 0x07];
520 pll->ct.mclk_fb_div = mclk_fb_div;
524 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per;
527 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 /
528 (pll->ct.mclk_fb_mult * par->xclk_per);
538 pll->ct.xclk_post_div_real = aty_postdividers[xpost_div];
539 pll->ct.mclk_fb_div = q * pll->ct.xclk_post_div_real / 8;
544 pll->ct.xclk_post_div = xpost_div;
545 pll->ct.xclk_ref_div = 1;
550 pllmclk = (1000000 * pll->ct.mclk_fb_mult * pll->ct.mclk_fb_div) /
551 (par->ref_clk_per * pll->ct.pll_ref_div);
553 __func__, pllmclk, pllmclk / pll->ct.xclk_post_div_real);
557 pll->ct.pll_gen_cntl = OSC_EN;
559 pll->ct.pll_gen_cntl = OSC_EN | DLL_PWDN /* | FORCE_DCLK_TRI_STATE */;
562 pll->ct.pll_ext_cntl = 0;
564 pll->ct.pll_ext_cntl = xpost_div;
566 if (pll->ct.mclk_fb_mult == 4)
567 pll->ct.pll_ext_cntl |= PLL_MFB_TIMES_4_2B;
570 pll->ct.pll_gen_cntl |= (xpost_div << 4); /* mclk == xclk */
576 pll->ct.pll_gen_cntl |= (6 << 4); /* mclk == sclk */
578 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per;
588 pll->ct.sclk_fb_div = q * sclk_post_div_real / 8;
589 pll->ct.spll_cntl2 = mpost_div << 4;
591 pllsclk = (1000000 * 2 * pll->ct.sclk_fb_div) /
592 (par->ref_clk_per * pll->ct.pll_ref_div);
599 pll->ct.ext_vpll_cntl = aty_ld_pll_ct(EXT_VPLL_CNTL, par);
600 pll->ct.ext_vpll_cntl &= ~(EXT_VPLL_EN | EXT_VPLL_VGA_EN | EXT_VPLL_INSYNC);
606 union aty_pll *pll)
618 aty_st_pll_ct(SCLK_FB_DIV, pll->ct.sclk_fb_div, par);
619 aty_st_pll_ct(SPLL_CNTL2, pll->ct.spll_cntl2, par);
627 aty_st_pll_ct(PLL_REF_DIV, pll->ct.pll_ref_div, par);
628 aty_st_pll_ct(PLL_GEN_CNTL, pll->ct.pll_gen_cntl, par);
629 aty_st_pll_ct(MCLK_FB_DIV, pll->ct.mclk_fb_div, par);
630 aty_st_pll_ct(PLL_EXT_CNTL, pll->ct.pll_ext_cntl, par);
631 aty_st_pll_ct(EXT_VPLL_CNTL, pll->ct.ext_vpll_cntl, par);